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VP306 Datasheet(PDF) 50 Page - Mitel Networks Corporation |
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VP306 Datasheet(HTML) 50 Page - Mitel Networks Corporation |
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50 / 85 page ![]() VP305/6 DRAFT - PRELIMINARY DATA The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 50 2.11. BANK 6: Program FEC and general control registers. 2.11.1. VIT_CTRL1: Viterbi control synchronisation byte register 1 Parallel mode - Bank 6. Address 1. Type Read / Write. Serial mode - Address 49. 7 6543210 BS_MODE[1:0] VS_UNLK[3:0] VBIT_MV[1:0] VBIT_MV[1:0] Viterbi synchronisation majority voting selection for the number of correct bits in a byte to have the byte labelled as a synchronisation byte. VBIT_MV[1:0] No. correct bits in sync 05 16 ← Recommended 27 38 Table 10. Number of correct bits in the sync byte. VS_UNLK[3:0] Viterbi sync majority voting selection for retaining sync lock. VIT_CTRL1 (weighted) VS_UNLK[3:0] No. syncs to keep lock 003 414 825 12 3 6 16 4 7 ← Recommended 20 5 8 24 6 9 28710 32811 36912 40 10 13 44 11 14 48 12 15 52 13 16 56 14 17 60 15 18 Table 11. Number of correct sync bytes to retain lock. |
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