VP306 datasheet(22/85 Pages) MITEL

22 / 85 page

VP305/6

DRAFT - PRELIMINARY DATA

The duplication or disclosure of data contained on this sheet is subject to the restrictions

on the title page of this document.

NAME

ADR

D7D6D5D4D3D2

D1D0

R/W

ID[7:0] Chip identification

VIT_MODE

IQSWAP F_LOCK

Reserved

VITCR[2:0] - code rate

R/W

VIT_ERR H

VITEP[23:16] - Viterbi error period high byte

R/W

VIT_ERR M

VITEP[15:8] - Viterbi error period middle byte

R/W

VIT_ERR L

VITEP[7:0] - Viterbi error period low byte

R/W

VI_MAX_ERR

VMERR[7:0] - Viterbi max. bit error count

R/W

VI_BER_PER

VBPER[7:0] - Viterbi bit error rate based synchronisation period

R/W

VI_BER_LIM

VBLIM[7:0] - Viterbi bit error rate based synchronisation limit

R/W

Table 5g. Register bank 5. BANK[5:3] = 40.

NAME

ADR

D7D6D5D4D3D2

D1D0

R/W

ID[7:0] Chip identification

VIT_CTRL1

BS_MODE[1:0]

VS_UNLK[3:0]

VBIT_MV[1:0]

R/W

VIT_CTRL2

Reserved

VS_LK[2:0]

R/W

IE_FEC

IE_FEC[7:0] Interrupt enable FEC

R/W

STAT_EN

STAT_EN[7:0] Enable various outputs on STATUS pin.

R/W

GEN_CTRL

MCLKINV

BSO

ENTEI

NSYNC[1:0]

R/W

GPP_CTRL

Reserved

GPP_CTRL[4:0]

R/W

RESET

RES

PR_DS

PR_BS

FR_QP

PR_QP R/W

Table 5h. Register bank 6. BANK[5:3] = 48.

NAME

ADR

D7D6D5D4D3D2

D1D0

R/W

ID[7:0] Chip identification

TEST1

Reserved

R/W

TEST2

INTVIS

EN[3:0]

R/W

TEST3

Reserved

R/W

Not used

4 - 7

Writing to these addresses will have no effect. Reading will return 255

R/W

Table 5i. Register bank 7. BANK[5:3] = 56.

Note: In Bank 7, the registers 4 - 7 are not used. Writing to these addresses will have no effect.

Note: When writing to, or reading from registers which are part of a group, all registers in the

group must be addressed for the data transfer to be sucessfully completed.

VP306 Datasheet(PDF) 22 Page - Mitel Networks Corporation

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