VP306 datasheet(74/85 Pages) MITEL

74 / 85 page

VP305/6

DRAFT - PRELIMINARY DATA

The duplication or disclosure of data contained on this sheet is subject to the restrictions

on the title page of this document.

6.5.

Pinout description.

Pin No

Name

Pin Description

I/O Note V mA

SER

A logic 1 selects the 8 bit interface, a logic 0 selects I²C

interface. Not connected on VP305.

ICMOS 5

PSCAL

Input from SL1710 (differential prescaler true output).

PECL

δ1

PSCAL

Input from SL1710 (differential prescaler inverted

output).

PECL

δ1

6-11

IIN5:0

In phase data input from the ADC digitiser.

TTL

14-19

QIN5:0

Quadrature phase data input from the ADC digitiser.

Input format is selected by bit CONFIG[0].

TTL

SYS_CLK System clock input.

TTL

Address select strobe. The address on pins A2:0 is

latched on the negative going edge.

ICMOS 5

Chip select for the microprocessor interface, a logic 0

makes the interface active. Data on pins D7:0 is latched

on the positive going edge.

ICMOS 5

25-27

A2:0

Address pins for the internal registers used with the 8 bit

interface.

ICMOS 5

DTACK

Data acknowledge. A logic 0 indicates data has been

transferred.

O Open

drain

R/ W

A logic 1 indicates a read operation, a logic 0 a write

operation.

ICMOS 5

IRQ

A low output on this pin indicates an event has occurred

and the microprocessor should read the interrupt

registers. A read of both interrupt registers resets this

pin.

O Open

drain

33,35-39,

42-43

D7:0

Data port for read or write data. D0 = SCL Clock input

for I²C when SER = logic 0.

I/O Open

drain

SDA

Data I/O pin for I²C. Not available on VP305 version.

I/O Open

drain

RESET

Active HIGH reset input, with 100k pull down resistor.

I CMOS 5

XTO

Crystal output. An internal feedback resistor to XTI is

included.

OCMOS 3.3

XTI

Crystal clock input or external reference clock input for

QPSK block.

ICMOS 3.3

STATUS

Output pin for various functions selected by register bits. O CMOS 3.3 1

MCLK

MPEG clock output at the data byte rate.

Tri-

state

3.3 1

63-60,

57-54

MDO7:0

MPEG transport packet data output bus.

Tri-

state

3.3 1

MDOEN

Logic 1 = MPEG data and clock outputs disable -

tristate. Logic 0 = MPEG data and clock outputs enable.

ICMOS 5

Pin No

Name

Pin Description

I/O Note V mA

VP306 Datasheet(PDF) 74 Page - Mitel Networks Corporation

VP306 Datasheet(HTML) 74 Page - Mitel Networks Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85

Datasheet Download

Link URL