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VP306 Datasheet(PDF) 2 Page - Mitel Networks Corporation |
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VP306 Datasheet(HTML) 2 Page - Mitel Networks Corporation |
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2 / 85 page ![]() VP305/6 DRAFT - PRELIMINARY DATA The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 2 CONTENTS. 1. FUNCTIONAL DESCRIPTION. ..............................................................................................7 1.1. System overview. ..........................................................................................................7 1.2. The QPSK Demodulator block. .....................................................................................9 1.2.1. Input requirements. .............................................................................................10 1.2.3. Matched filters.....................................................................................................10 1.2.4. Decimation filters.................................................................................................10 1.2.5. Carrier frequency synchronisation ......................................................................11 1.2.6. Symbol synchronisation and tracking..................................................................12 1.3. The Viterbi Decoder block. ............................................................................................13 1.3.1. Viterbi error count measurement.........................................................................14 1.3.2. Viterbi error count coarse indication....................................................................15 1.4. The De-interleaver block. ..............................................................................................16 1.5. The Reed Solomon block. .............................................................................................18 1.6. The Energy Dispersal (descrambler) block. ..................................................................18 1.6.1. Output stage........................................................................................................19 1.7. Microprocessor interface. ..............................................................................................19 2. REGISTER DETAILS .............................................................................................................20 2.1. Parallel interface register map. .....................................................................................20 2.2. Serial interface register map. ........................................................................................23 2.3. BANK: Register bank address - Parallel mode only......................................................25 2.4. RADD: I²C Register address - Serial mode only. ..........................................................26 2.5. BANK 0: Monitor QPSK read registers..........................................................................27 2.5.1. ID: Identification register. ....................................................................................27 2.5.2. INT_QPSK: Interrupt for QPSK block, register....................................................27 2.5.3. INT_FEC: Interrupt FEC register.........................................................................28 2.5.4. STATUS: Status register. ....................................................................................29 2.5.5. AGC_LVL: AGC loop voltage meter register.......................................................30 2.5.6. CR_VCOF U & L: Measured VCO frequency registers. ......................................30 2.5.7. IE_QPSK: Interrupt enable QPSK register..........................................................31 2.6. BANK 1: Program QPSK registers. ...............................................................................32 2.6.1. SYM_CONFIG: Symbol configuration register. ...................................................32 2.6.2. SYM_RP: Symbol AFC reference period register. ..............................................33 2.6.3. SYM_NF U & L: Symbol input nominal frequency registers. ...............................33 |
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