VP306 datasheet(11/85 Pages) MITEL

11 / 85 page

DRAFT - PRELIMINARY DATA

VP305/6

The duplication or disclosure of data contained on this sheet is subject to the restrictions

on the title page of this document.

SYM_RATIO

123

SYM_DR

samples/Sym

0 - (over sample 2)

1 - (over sample 4)

2 - (over sample 3)

Table 1. Decimation ratios.

1.2.5.

Carrier frequency synchronisation

The SL1710 local oscillator frequency of 479.5MHz is maintained by a frequency synthesis loop

on the VP305/6. The SL1710 voltage controlled oscillator (VCO) frequency is divided internally by

32 to generate a push-pull feedback reference frequency signal. This is connected to the VP305/6

PSCAL PECL inputs and then to the CR_U/LSWL dividers. The output from the CR_U/LSWL

dividers is compared with the crystal oscillator frequency divided by the CR_RP division ratio. A

feedback signal (CR_VCO) is output to an active filter to complete the loop and control the

SL1710 VCO, see Fig. 3 on page 9.

The internal frequency sweep generator is controlled by the CR_SWR, CR_USWL,CR_LSWL,

CR_RP registers and turned on and off by the CR_SW bit in the CONFIG register. The diagram in

Fig. 3 on page 9 shows the registers which set up the dividers for both the carrier and symbol

phase locked loops.

Upper

Sweep

Limit

Lower

Sweep

Limit

Sweep

Start

Point

Fig. 6. Frequency sweep generator.

The carrier frequency reference period (CR_RP register) sets the count of the crystal clock cycles

(XTI pin). This sets the reference for the measurement of the I/Q down converter VCO frequency

(PSCAL pins). The register value sets the 4 most significant bits of a 14 bit counter. The actual

count is CR_RP[3:0] * 1024.

VP306 Datasheet(PDF) 11 Page - Mitel Networks Corporation