VP306 datasheet(52/85 Pages) MITEL

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VP305/6

DRAFT - PRELIMINARY DATA

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2.11.3.

IE_FEC: Interrupt FEC register.

When the bits of this register are set high, they enable an event signalled in the INT_FEC register

to generate an interrupt on the IRQ pin. They do not affect the setting of bits in the INT_FEC

Parallel mode -

Bank 6. Address 3.

Type Read / Write.

Serial mode - Address 51.

76543210

IE_FEC[7:0] Interrupt enable FEC

When :

IE_FEC[i] =1 : enable INT_FEC[i]

IE_FEC[i] =0 : disable INT_FEC[i] (default state)

where i = 0 to 7.

IE_FEC[0]

High = Enable Descrambler lock established indication in INT_FEC register.

IE_FEC[1]

High = Enable Descrambler lock lost indication in INT_FEC register.

IE_FEC[2]

High = Enable Viterbi error period indication in INT_FEC register.

IE_FEC[3]

Reserved set low.

IE_FEC[4]

High = Enable Viterbi bit lock established indication in INT_FEC register.

IE_FEC[5]

High = Enable Viterbi bit lock lost indication in INT_FEC register.

IE_FEC[6]

High = Enable Frame alignment lock established indication in INT_FEC register. (A

Frame is 8 blocks, each block is 204 bytes).

IE_FEC[7]

High = Enable Frame alignment lock lost indication in INT_FEC register.

VP306 Datasheet(PDF) 52 Page - Mitel Networks Corporation