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TDC-GP21 Datasheet(PDF) 48 Page - ams AG |
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TDC-GP21 Datasheet(HTML) 48 Page - ams AG |
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48 / 91 page  TDC-GP21 acam messelectronic gmbh - Friedrich-List-Str.4 - 76297 Stutensee - Germany - www.acam.de 4-3 a. Select measurement mode 1 Set register 0, bit 11, MESSB2 = 0. Register 6, bit 12, DOUBLE_RES = 1 selects double resolution. With this bit set the resolution is typ. 45 ps instead of 90 ps, but only one STOP channel is available. b. Select the reference clock (see also section 5.1) Register 0, bits 18 & 19 and register 6, bit 20, START_CLKHS defines the switch-on behavior of the high-speed clock. If only the 32 kHz is used it should be “0“. If only the high-speed clock is used it should be “1“ (continuously on). Register 0, bits 20 & 21, DIV_CLKHS sets an additional internal divider for the reference clock (1, 2 or 4). This is important for calibrated measurements in measurement mode 1 because the ALU works correctly only if 2*Tref(intern) is bigger than the maximum time interval to be measured. Otherwise the ALU output is ’hFFFFFFFF. Make also sure that 2*Tref(intern) < 2.4 µs to avoid a timeout during calibration. c. Set the number of expected hits In register 1, bits 16 to 18 and 19 to 21, HITIN1 and HITIN2 the user has to define the number of hits the TDC-GP21 has to wait for. A maximum of 4 on each channel is possible. The TDC-GP21 measures until the set number of hits is registered or a timeout occurs. d. Select calibration Figure 4.3 Member of the ams Group |
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