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CDCE62005 Datasheet(PDF) 29 Page - Texas Instruments

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Part # CDCE62005
Description  3:5 Clock Generator
PDF  85 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCE62005 Datasheet(HTML) 29 Page - Texas Instruments

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/2-/5
/1 - /8
/2
From
Output
MUX
To
Output
Buffer
16
Registers 0 - 4
Registers 0 - 4
18
19
01
10
00
Prescaler
IntegerDivider
15
17
13
Registers 0 - 4
14
OutputDivider (7-bits)
DigitalPhase Adjust (7-bits)
Sync
Pulse
(internallygenerated )
Enable
From
Output
MUX
To
Output
Buffer
20
Registers 0 - 4
6
Registers 0 - 4
7
8
9
10
11
12
13
Registers 0 - 4
14
15
16
17
18
19
CDCE62005
www.ti.com
SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015
8.3.5.10 Output Dividers
Figure 23 shows that each output channel provides a 7-bit divider and digital phase adjust block. The Table 13
lists the divide ratios supported by the output divider for each output channel. Figure 24 illustrates the output
divider architecture in detail. The Prescaler provides an array of low noise dividers with duty cycle correction. The
Integer Divider includes a final divide by two stage which is used to correct the duty cycle of the /1–/8 stage. The
output divider’s maximum input frequency is limited to 1.175 GHz. If the divider is bypassed (divide ratio = 1)
then the maximum frequency of the output channel is 1.5 GHz.
Figure 23. CDCE62005 Output Divider and Phase Adjust
Figure 24. CDCE62005 Output Divider Architecture
Copyright © 2008–2015, Texas Instruments Incorporated
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