CDCE62005 datasheet(49/85 Pages) TI1

49 / 85 page

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L,R

L,A

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CDCE62005

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SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015

The normalized frequency error of the crystal, as a result of load capacitance mismatch, can be calculated as

Equation 8:

where

•

Δf is the frequency error of the crystal

•

f is the rated frequency of the crystal

•

CS is the motional capacitance of the crystal

•

CL,R is the rated load capacitance for the crystal

•

CO is the shunt capacitance of the crystal

•

CL,A is the actual load capacitance in the implemented PCB for the crystal

(8)

The first three parameters can be obtained from the crystal vendor.

In order to minimize the frequency error of the crystal to meet application requirements, the difference between

the rated load capacitance and the actual load capacitance should be minimized and a crystal with low-pull

capability (low CS) should be used.

For example, if an application requires less than ±50 ppm frequency error and a crystal with less than ±50 ppm

frequency tolerance is picked, the characteristics are as follows: C0 = 7 pF, CS = 10 µF, and CL,R = 12 pF. In

order to meet the required frequency error, calculate CL,A using Equation 8 to be 17 pF. Subtracting CL,R from

CL,A, results in 5 pF. Take care to ensure that the sum of the crystal stray capacitance and board parasitic

capacitance is less than the calculated 5 pF during printed circuit board (PCB) layout with the crystal and the

CDCE62005. Good layout practices are fundamental to the correct operation and reliability of the oscillator. It is

critical to locate the crystal components very close to the XIN pin to minimize routing distances. Long traces in

the oscillator circuit are a very common source of problems. Do not route other signals across the oscillator

circuit. Also, make sure power and high-frequency traces are routed as far away as possible to avoid crosstalk

and noise coupling. Avoid the use of vias; if the routing becomes very complex, it is better to use 0-

Ω resistors as

bridges to go over other signals. Vias in the oscillator circuit should only be used for connections to the ground

plane. Do not share ground connections; instead, make a separate connection to ground for each component

that requires grounding. If possible, place multiple vias in parallel for each connection to the ground plane.

Especially in the Colpitts oscillator configuration, the oscillator is very sensitive to capacitance in parallel with the

crystal. Therefore, the layout must be designed to minimize stray capacitance across the crystal to less than 5 pF

total under all circumstances to ensure proper crystal oscillation. Be sure to take into account both PCB and

crystal stray capacitance.

8.3.8 VCO Calibration

The CDCE62005 includes two on-chip LC oscillator-based VCOs with low phase noise covering a frequency

range of 1.75 GHz to 2.356 GHz. The VCO must be calibrated to ensure proper operation over the valid device

operating conditions. VCO calibration is controlled by the reference clock input. This calibration requires that the

PLL be set up properly to lock the PLL loop and that the reference clock input be present.

The device enters self-calibration of the VCO automatically at power up at device default mode, after the

registers have been loaded from the EEPROM and an input clock signal is detected. If there is no input clock

available during power up, the VCO will wait for the reference clock before starting calibration.

If the input signal is not valid during self-calibration, it is necessary to re-initiate VCO calibration after the input

clock signal stabilizes.

NOTE

Re-calibration is also necessary anytime a PLL setting is changed (for example, divider

ratios in the PLL or loop filter settings are adjusted).

VCO calibration can be initiated by writing to register 6 bits 27 and 22 or register 8 bit 7 (/SLEEP bit).

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