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CDCE62005 Datasheet(PDF) 39 Page - Texas Instruments

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Part # CDCE62005
Description  3:5 Clock Generator
PDF  85 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCE62005 Datasheet(HTML) 39 Page - Texas Instruments

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OutputDivider 2
OutputDivider 3
AUX
OUT
Register 6
25
Register 6
24
CDCE62005
www.ti.com
SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015
Table 20. Output Synchronization Procedure
R4.1
R6.20
COMMENTS
0
0
The synchronized outputs will be enabled after ~6 µs delay and the next rising edge of the
reference clock and selected clock of output multiplexer.
0
1
The synchronized outputs will be enabled after ~6 µs delay and the next rising edge of
Toggling SYNC Pin or
selected clock of output multiplexer (reference Figure 26 (a)).
Bit (R8.8) from low to
1
0
The synchronized outputs will be enabled with the next rising edge of reference clock & the
high
selected clock of output multiplexer (reference Figure 26 (c)).
1
1
The synchronized outputs will be enabled with the next rising edge of the selected clock of
output multiplexer (reference Figure 26 (b)).
Toggling SYNC Pin or
X
X
All outputs are disabled.
Bit (R8.8) from high to
low
8.3.5.15 Auxiliary Output
Figure 27 shows the auxiliary output port. Table 21 lists how the auxiliary output port is controlled. The output
buffer supports a maximum output frequency of 250 MHz and drives at LVCMOS levels. Refer to Table 13 for the
list of divider settings that establishes the output frequency.
Figure 27. CDCE62005 Auxiliary Output
Table 21. CDCE62005 Auxiliary Output Settings
BIT NAME
→
AUXFEEDSEL
AUXOUTEN
AUX OUTPUT SOURCE
REGISTER.BIT
→
6.25
6.24
X
0
OFF
0
1
Divider 2(1)
1
1
Divider 3(1)
(1)
If Divider 2 or Divider 3 is set to divide by 1 and AUXOUT is selected from divide by 1, then AUXOUT
will be disabled even if the AUXOUTEN bit (6.24) is high.
Copyright © 2008–2015, Texas Instruments Incorporated
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