CDCE62005 datasheet(48/85 Pages) TI1

48 / 85 page

CDCE62005

SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015

www.ti.com

Table 34. CDCE62005 Lock Detect Window

DIGITAL LOCK DETECT

BIT NAME

→

LOCKW(3)

LOCKW(2)

LOCKW(1)

LOCKW(0)

→

5.25

5.24

5.23

5.22

LOCK DETECT WINDOW

1.5 ns

5.8 ns

15.1 ns

Reserved

3.4 ns

7.7 ns

17.0 sn

Reserved

5.4 ns

9.7 ns

19.0 ns

Reserved

15.0 ns

19.3 ns

28.6 ns

Reserved

8.3.7 Crystal Input Interference

Fundamental mode is the recommended oscillation mode of operation for the input crystal and parallel

resonance is the recommended type of circuit for the crystal.

A crystal load capacitance refers to all capacitances in the oscillator feedback loop. It is equal to the amount of

capacitance seen between the terminals of the crystal in the circuit. For parallel resonant mode circuits, the

correct load capacitance is necessary to ensure the oscillation of the crystal within the expected parameters.

The CDCE62005 implements an input crystal oscillator circuitry, known as the Colpitts oscillator, and requires

one pad of the crystal to interface with the AUX IN pin; the other pad of the crystal is tied to ground. In this

crystal interface, it is important to account for all sources of capacitance when calculating the correct value for

the discrete capacitor component, CL, for a design.

The CDCE62005 has been characterized with 10-pF parallel resonant crystals. The input crystal oscillator stage

in the CDCE62005 is designed to oscillate at the correct frequency for all parallel resonant crystals with low-pull

capability and rated with a load capacitance that is equal to the sum of the on-chip load capacitance at the AUX

IN pin (10-pF), crystal stray capacitance, and board parasitic capacitance between the crystal and AUX IN pin.

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