CDCE62005 datasheet(38/85 Pages) TI1

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Delay

~6µs

SYNC#

R4.1

R6.20

Selected Reference Input

R0[4:5]

Output

Divider

Output

Divider

R4[4:5]

SYNC#

Bit (R8.8)

Reference Clock

PreScalar Clock

SYNC

Output

( R4.1=0 & R6.20=1)

Output

( R4.1=1 & R6.20=0)

Output

( R4.1=1 & R20.6=1)

Tristate

( a )

( b )

( c )

next rising edge

next PreScaler CLK

Tristate

~ 6 µ s

next PreScaler CLK

CDCE62005

SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015

www.ti.com

8.3.5.14

Output Synchronization

Figure 26 shows the output synchronization circuitry and relative output clock phase position with respect to

SYNC signal Low to High phase transition.

NOTE: The signal diagram is based on the assumption that prescalar clock is selected by output Mux ( Rn[4:5] where n = 0,

1, 2, 3 or 4)

Figure 26. Output Synchronization Diagram

The synchronization of the outputs can be accomplished by toggling the SYNC pin, or Bit (R8.8), or by changing

any output divider values. Table 20 shows the phase relationship between output phase and the SYNC signal,

the selected reference clock and the prescalar output clock phases.

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