CDCE62005 datasheet(63/85 Pages) TI1

63 / 85 page

CDCE62005

www.ti.com

SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015

8.6.3 Device Registers: Register 2 Address 0x02

Table 42. CDCE62005 Register 2 Bit Definitions

RAM BIT

BIT NAME

DESCRIPTION/FUNCTION

BLOCK

REFDIV0

Reference Divider Bit 0

EEPROM

Reference

Divider

REFDIV1

Reference Divider Bit 1

EEPROM

RESERVED

Must be set to 0

EEPROM

RESERVED

Must be set to 0

EEPROM

OUTMUX2SELX

Output 2

OUTPUT MUX 2 Select. Selects the Signal driving Output Divider 2

EEPROM

(X,Y) = 00: PRI_REF, 01:SEC_REF, 10:SMART_MUX, 11:VCO_CORE

OUTMUX2SELY

Output 2

EEPROM

PH2ADJC0

Output 2

EEPROM

PH2ADJC1

Output 2

EEPROM

PH2ADJC2

Output 2

EEPROM

PH2ADJC3

Output 2

Coarse phase adjust select for output divider 2

EEPROM

PH2ADJC4

Output 2

EEPROM

PH2ADJC5

Output 2

EEPROM

PH2ADJC6

Output 2

EEPROM

OUT2DIVRSEL0

Output 2

EEPROM

OUT2DIVRSEL1

Output 2

EEPROM

OUT2DIVRSEL2

Output 2

EEPROM

OUT2DIVRSEL3

Output 2

OUTPUT DIVIDER 2 Ratio Select

EEPROM

OUT2DIVRSEL4

Output 2

EEPROM

OUT2DIVRSEL5

Output 2

EEPROM

OUT2DIVRSEL6

Output 2

EEPROM

When set to 0, the divider is disabled

OUT2DIVSEL

Output 2

EEPROM

When set to 1, the divider is enabled

High Swing LVPECL When set to 1 and Normal Swing when set to 0.

– If LVCMOS or LVDS is selected the Output swing will stay at the same level.

(1)

HiSWINGLVPEC2

Output 2

EEPROM

– If LVPECL buffer is selected the Output Swing will be 30% higher if this bit is set to 1 and Normal LVPECL if

it is set to 0.

CMOSMODE2PX

Output 2

LVCMOS mode select for OUTPUT 2 Positive Pin.

EEPROM

(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State

CMOSMODE2PY

Output 2

EEPROM

CMOSMODE2NX

Output 2

LVCMOS mode select for OUTPUT 2 Negative Pin.

EEPROM

(X,Y)=00:Active, 10:Inverting, 11:Low, 01:3-State

CMOSMODE2NY

Output 2

EEPROM

OUTBUFSEL2X

Output 2

OUTPUT TYPE

RAM BITS

EEPROM

LVPECL

LVDS

OUTBUFSEL2Y

Output 2

EEPROM

LVCMOS

See Settings Above

Output Disabled

* Use Description for Bits 22,23,24 and 25 for setting the LVCMOS Outputs

(1)

Set the R2.21 to 0 for LVDS and LVCMOS outputs

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