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CDCE62005 Datasheet(PDF) 16 Page - Texas Instruments

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Part # CDCE62005
Description  3:5 Clock Generator
PDF  85 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCE62005 Datasheet(HTML) 16 Page - Texas Instruments

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/1:/2:HiZ
/1:/2:HiZ
Reference Divider
/1 - /8
PRI_REF
SEC_REF
XTAL/
AUX IN
1500 MHz
LVPECL: 1500 MHz
LVDS: 800 MHz
LVCMOS: 250 MHz
1500 MHz
Crystal: 2 MHz - 42 MHz
Smart
MUX1
Smart
MUX2
Smart MUX
Control
REF_SEL
CDCE62005
SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015
www.ti.com
Functional Block Diagrams (continued)
8.2.2 Input Block
The Input Block includes a pair of Universal Input Buffers and an Auxiliary Input. The Input Block buffers the
incoming signals and facilitates signal routing to the Internal Clock Distribution bus and the Synthesizer Block via
the smart multiplexer (called the Smart MUX). The Internal Clock Distribution Bus connects to all output blocks
discussed in the next section. Therefore, a clock signal present on the Internal Clock Distribution bus can appear
on any or all of the device outputs. The CDCE62005 routes the PRI_REF and SEC_REF inputs directly to the
Internal Clock Distribution Bus. Additionally, it can divide these signals via the dividers present on the inputs and
output of the first stage of the Smart MUX.
Figure 12. CDCE62005 Input Block
16
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Product Folder Links: CDCE62005



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