CDCE62005 datasheet(74/85 Pages) TI1

74 / 85 page

CDCE62005

SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015

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10 Power Supply Recommendations

The CDCE62005 is a high performance device. Therefore careful attention must be paid to device configuration

and printed circuit board layout with respect to power consumption. Table 49 provides the power consumption for

the individual blocks within the CDCE62005. To estimate total power consumption, calculate the sum of the

products of the number of blocks used and the power dissipated of each corresponding block.

Table 49. CDCE62005 Power Consumption

INTERNAL BLOCK POWER AT 3.3V (typ.)

POWER DISSIPATION/ BLOCK

NUMBER OF BLOCKS

Input Circuit

250 mW

PLL and VCO Core

500 mW

Divider = 1

60 mW

Output Dividers

Divider > 1

180 mW

LVPECL Output Buffer

75 mW(1)

LVDS Output Buffer

76 mW

Static

7 mW

LVCMOS Output Buffer Transient, C

L = load, fOUT = MHz output

3.3 × V × fOUT × (CL + 20 × 10

-12) ×

frequency, V = output swing

103

(1)

An additional ~50 mW of power is dissipated externally at the termination resistors per LVPECL output pair.

This power estimate determines the degree of thermal management required for a specific design. Employing the

thermally enhanced printed circuit board layout shown in Figure 53 ensures that the thermal performance curves

shown in Figure 52 apply. Observing good thermal layout practices enables the thermal pad on the backside of

the QFN-48 package to provide a good thermal path between the die contained within the package and the

ambient air. This thermal pad also serves as the ground connection the device. Therefore, a low inductance

connection to the ground plane is essential.

Figure 53 shows a layout optimized for good thermal performance and a good power supply connection as well.

The 7×7 filled via pattern facilitates both considerations. Finally, the recommended layout achieves RθJA =

27.3°C/W in still air and 20.3°C/W in an environment with 100 LFM airflow if implemented on a JEDEC compliant

thermal test board..

Figure 52. CDCE62005 Die Temperature vs Total Device Power

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