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S6J32BA Datasheet(PDF) 16 Page - Cypress Semiconductor |
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S6J32BA Datasheet(HTML) 16 Page - Cypress Semiconductor |
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16 / 179 page  Document Number: 002-05682 Rev.*A Page 16 of 179 S6J3200 Series Feature Description Sound Mixer The input channels of 0 - 4 are reserved for waveform generator. Mixing different sampling frequency sounds. Mixing Internal sounds and External I2S input sounds. Saturating addition function for keeping sound quality. Cut a specific frequency data by digital filter. LPF is support by FIR filter. Fade-in and Fade-out control. PCM-PWM Conversion of PCM audio streaming to Pulse Width Modulated signals. Supports 2 output channels for stereo and mono data Up to 16-bit output sample resolution Support for half and full H-bridges Audio DAC The sound source of the fixed 48kHz sampling frequency can be outputted. 1unit, L/R channels support. BTL connection is available. I2S 2ch. − I2S0 can output sound sources which are processed by Sound System. − I2S1 can input sound sources which are processed by Sound System. − I2S has its own PPU, but the function is fixed to disable. See the "Sound System Configuration" of S6J3200 hardware manual in detail. Base Timer See the platform manual in detail. A unit consists of a pair of 16bit base timers. 12 units, that is, 24 channels of base timers are available. Reload Timer See the platform manual in detail. I/O Timer See the platform manual in detail. Quad Position & Revolution Counter (Up/Down Counter) See the platform manual in detail. Multi-functional Serial (MFS) See the platform manual in detail. 2 ports of MFS only support I 2C. Note − Not all pins support I2C. Only pins which have the I2C I/O characteristics support it. See the datasheet in detail. The availability of chip select function can be seen at Function Digit Table. Chip Select Input is not supported. CTS/RTS is not mounted (hardware flow control is not supported for this series.) WUCR function is not supported for this product. CAN-FD Flexible data rate is supported. 16KB/ch of message RAM is available. The clock output from CAN pre-scaler is supplied to every CAN. ECC error generation function of the message RAM is not supported for this device. Therefore CAN FD ECC Error Insertion Control Register (FDFECR) is not writeable. See the platform manual in detail Real Time Clock (RTC) with Auto-calibration See the platform manual in detail. DDR High Speed SPI ch.0: HSSPI as a MCU peripheral ch.1: HSSPI on graphic subsystem See the platform manual in detail |
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