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PC87591L Datasheet(PDF) 333 Page - National Semiconductor (TI) |
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PC87591L Datasheet(HTML) 333 Page - National Semiconductor (TI) |
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333 / 437 page ![]() Host Controller Interface Modules (Continued) Revision 1.07 333 www.national.com MSWC Host Event Interrupt Enable Register (MSHEIE0) This register is cleared to 0016 on Warm reset. It enables a core interrupt through the MIWU (level high) for the respective bit in the mobile MSHES0 register. The interrupt may be cleared by clearing the status bit or masking the interrupt. Location: Offset 00 FCD016 Type: R/W 3 RING Event Status. RING event detection, according to the RING detection mode enabled. 0: Event not detected (default) 1: Event detected 5-4 Reserved. 6 Software Event Status. This bit indicates a host software event. It may operate in two modes depending on HSECM bit in MSWCTL1 register. When HSECM is cleared, this bit is set when bit 6 of WK_STS0 changes from 0 to 1. When HSECM is set, this bit is set on a write of 1 to WK_STS0 bit 1. This bit is cleared by writing 1 to it. 0: Event not active (default) 1: Event active 7 Module IRQ Event Status. This sticky bit shows the status of the module IRQ event detection. 0: Event not active (default) 1: Event active Bit 76543210 Name Module IRQ Event Enable Software Event Enable Reserved RING Event Enable Reserved RI2 Event Enable RI1 Event Enable Reset 00000000 Bit Description 0 RI1 Event Enable. 0: Disabled (default) 1: Enabled 1 RI2 Event Enable. 0: Disabled (default) 1: Enabled 2 Reserved. 3 RING Event Enable. 0: Disabled (default) 1: Enabled 5-4 Reserved. 6 Software Event Enable. 0: Disabled (default) 1: Enabled 7 Module IRQ Event Enable. 0: Disabled (default) 1: Enabled Bit Description |
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