PC87591L datasheet(331/437 Pages) NSC

331 / 437 page

Host Controller Interface Modules (Continued)

Revision 1.07

331

www.national.com

Host Conﬁguration Base Address Low (HCFGBAL)

This is a byte-wide read/write register that holds the lower byte of the Host Configuration Registers base address. Bit 0 of

this register is always forced to 0 to guarantee address alignment. This register is cleared on VCC Power-Up reset.

Location: 00 FCC816

Type: R/W

Host Conﬁguration Base Address High (HCFGBAH)

This is a byte-wide read/write register that holds the higher byte of the Host Configuration Registers base address. This reg-

ister is cleared on VCC Power-Up reset.

Location: 00 FCCA16

Type: R/W

MSWC Interrupt Enable Register 2 (MSIEN2)

This is a byte-wide read/write register that holds enable bits for interrupt generation to the core through the MIWU (level high)

for the respective bits in MSWCTL2 and MSWCTL3 registers. The interrupt may be cleared by clearing the status bit or

masking the interrupt. On Warm reset, this register is cleared (0016).

Location: 00 FCCC16

Type: R/W

Bit

Description

HRAPU (Host Reset when Accessed During VCC Power-Up Reset). Indicates that a reset should be sent to

the host if LPC activity was detected while the VCC Power-Up reset was not completed. This intends to re-start

any LPC transaction that may have addressed the PC87591x but could not be handled correctly. When

HCFGLK bit is set, writes to this bits are ignored.

0: Do not generate a reset on LPC transactions while the PC87591x is in Power-Up reset

1: Assert KBRST output on LPC transactions while the PC87591x is executing the VCC Power-Up reset sequence

(default)

LPFTO (LPC Power Fail Turn Off KBRST and GA20). Indicates the handling of KBRST and GA20 outputs

when LPCPD is active.

0: Ignore LPCPD in handling these signals (default)

1: Force the two signals low while LPCPD is active or VDD is low

RTCAL (RTC Alarm). Indicates that an RTC Alarm event occurred. This bit is set on the rising edge of the RTC

Alarm output. It is cleared by writing 1 to it. Note that the ALARM event detection is edge triggered by the

RTCAL bit; thus for a new event to be detected, ﬁrst RTCAL bit and then Alarm Status bit in the RTC must be

cleared.

0: No RTC Alarm is flagged (default)

1: RTC Alarm rising edge was detected

7-3

Reserved.

Bit

76543210

Name

Host Conﬁguration Registers Base Address Low

Reset

00000000

Bit

76543210

Name

Host Conﬁguration Registers Base Address High

Reset

00000000

PC87591L Datasheet(PDF) 331 Page - National Semiconductor (TI)

PC87591L Datasheet(HTML) 331 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL