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PC87591L Datasheet(PDF) 328 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # PC87591L
Description  LPC Mobile Embedded Controllers
PDF  437 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87591L Datasheet(HTML) 328 Page - National Semiconductor (TI)

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Host Controller Interface Modules (Continued)
www.national.com
328
Revision 1.07
Wake-Up Event Routing to IRQ Enable Register 0 (WK_IRQEN0)
This register is set to 0016 on VPP power-up or Host Domain Software reset. It controls the routing of detected wake-up
events to the assigned MSWC interrupt request (IRQ) channel. Detected wake-up events that are enabled activate the as-
signed IRQ channel regardless of the value of WK_EN0 register.
Location: Bank 2, Offset 1516
Type: R/W
5.5.6
MSWC Core Registers
For a summary of the abbreviations used for Register Type, see Section 2 on page 34.
Table 46. MSWC Core Register Map
Bit
76543210
Name
Reserved
Software
Event to
IRQ Enable
Reserved
RING
Event to
IRQ Enable
Reserved
RI2
Event to
IRQ Enable
RI1
Event to
IRQ Enable
Reset
00000000
Bit
Description
0
RI1 Event to IRQ Enable.
0: Disabled (default)
1: Enabled
1
RI2 Event to IRQ Enable.
0: Disabled (default)
1: Enabled
2
Reserved.
3
RING Event to IRQ Enable.
0: Disabled (default)
1: Enabled
5-4
Reserved.
6
Software Event to IRQ Enable.
0: Disabled (default)
1: Enabled
7
Reserved.
Mnemonic
Register Name
Type
MSWCTL1
MSWC Control Status Register 1
Varies per bit
MSWCTL2
MSWC Control Status Register 2
Varies per bit
MSWCTL3
MSWC Control Status Register 3
R/W
HCFGBAL
Host Configuration Base Address Low
R/W
HCFGBAH
Host Configuration Base Address High
R/W
MSIEN2
MSWC Interrupt Enable Register 2
R/W
MSHES0
MSWC Host Event Status Register 0
R/W1C
MSHEIE0
MSWC Host Event Interrupt Enable Register
R/W



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