PC87591L datasheet(330/437 Pages) NSC

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Host Controller Interface Modules (Continued)

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MSWC Control Status Register 2 (MSWCTL2)

This is a byte-wide read/write register that controls the settings associated with host wake-up and activity. Bits in this register

are cleared by VCC Power-Up and RESET1 resets.

Location: 00 FCC216

Type: Varies per bit

MSWC Control Status Register 3 (MSWCTL3)

This is a byte-wide read/write register that controls the settings associated with host wake-up and activity. The contents of

this register is preserved by VPP and it is reset only on VPP Power-Up reset.

Location: 00 FCC416

Type: R/W

Bit

76543210

Name

CFGPSO

CFGPBM

ACPIS5

ACPIS4

ACPIS3

ACPIS2

ACPIS1

ACPIS0

Reset

00000000

Bit

Type

Description

R/W1C ACPIS0 (ACPI request for S0). This bit may be used by ACPI software to directly request a change of

power state. This bit is set when the host software writes a value of 0 to bits S1 through S5 in

WK_STATE register. This bit is cleared by writing 1 to it. A write of 0 is ignored.

0: No pending request for S0 change (default)

1: A request for S0 change was detected

5-1

R/W1C ACPIS1-5 (ACPI request for S1 through S5). These bits may be used by ACPI software to directly

request a change of power state. These bits are set by a host software write of 1 to the respective bit in

WK_STATE register. The bit is cleared by writing 1 to it. A write of 0 is ignored.

When any ACPIS0 through ACPIS5 bit is set, an APC interrupt to the core, using a MIWU input, is

asserted.

6RO

CFGPBM (SuperI/O Conﬁguration Register D Power Button Mode). This bit reﬂects the current status

of the Power Button Mode bit in SIOCFD register. This bit may be used by the host software to specify

to the core he method used for power off signaling. See “SuperI/O Conﬁguration D Register (SIOCFD)”

on page 347

A write of 1 clears the interrupt signal caused by a change in this bit value. A write of 0 to this bit is

ignored.

7RO

CFGPSO (SuperI/O Conﬁguration Register D Power Supply Off). This bit is set whenever a 1 is

written to the Power Supply Off bit in SIOCFD register. This bit may be used by the host software to

specify to the core that the power supply should be turned off, in a non-ACPI system. See “SuperI/O

Conﬁguration D Register (SIOCFD)” on page 347.

A write of 1 clears this bit and the interrupt signal caused by a change in this bit value. A write of 0 to

this bit is ignored.

Bit

76543210

Name

Reserved

RTCAL

LPFTO

HRAPU

Reset

00000001

PC87591L Datasheet(PDF) 330 Page - National Semiconductor (TI)

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