PC87591L datasheet(329/437 Pages) NSC

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Host Controller Interface Modules (Continued)

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MSWC Control Status Register 1 (MSWCTL1)

This is a byte-wide read/write register that controls the settings associated with host wake-up and activity. The contents of

this register are preserved by VCC. Bit 0 is cleared by Warm reset; other bits are reset only on VCC Power-Up reset.

Location: 00 FCC016

Type: Varies per bit

Bit

76543210

Name

Reserved

HSECM

HCFGLK

VHCFGA

LPCRSTA

HPWRON

HRSTOB

Reset

000000

Bit

Type

Description

R/W

HRSTOB (Host Reset Out Bit). Enables the PC87591x to generate a Host Soft reset via ﬁrmware,

using the KBSTO pin. The pin is held low (reset is active) for as long this bit 1.

0: KBRST is not forced active (default)

1: Force KBRST active

1RO

HPWRON (Host Power On). The VDD power detection logic indicates that VDD is on.

0: VDD is off (below VDDON)

1: VDD is on (above VDDON)

2RO

LPCRSTA (LPC Reset Active). The RESET1 input is active (low).

0: RESET1 is not active (high)

1: RESET1 is active (low)

R/W1C VHCFGA (Valid Host Conﬁguration Address). This bit is set by a write to HCFGBAH register, as

detailed in the update sequence in “Host Conﬁguration Address Selection” on page 322. The ﬁrmware

can clear the bit by writing 1 to it. This register is used as the address of the Conﬁguration registers

when the PC87591x is set to operate with the internal base address. Writing 0 to this bit is ignored.

This bit can be locked and made read-only by setting HCFGLK (bit 4).

0: Host Configuration Registers base address is not valid and access to this registers by the host is not

enabled (default)

1: Host Configuration Registers base address is specified in HCFGBAH and HCFGBAL registers

R/W1S HCFGLK (Host Conﬁguration Address Lock). This bit is cleared during VCC power-up,

WATCHDOG reset or Debugger Interface reset, but is unchanged during other reset events.

When 1 is written to this bit, it becomes read only (i.e., it cannot be cleared by the ﬁrmware) and locks

VHCFGA bit, HCFGBAH register and HCFGBAL register, preventing accidental alteration to them.

0: Allows update of the Host Configuration Registers base address (default)

1: Locks the Host Configuration Registers base address

R/W1C HSECM (Host Software Event Clear Mode). Controls the clear mode of Host Software Event Status

bit in WK_STS0. This bit is cleared at VCC power-up and RESET1 events.

0: Host Software Event Status bit in WK_STS0 (bit 6) toggles on host writes of 1. MSHES0 bit 6 is set

when WK_STS0 bit 6 changes from 0 to 1 (default).

1: Host Software Event Status bit in WK_STS0 (bit 6) and MSHES0 bit 6 are both cleared by writes of

1 to MSHES0 register

7-6

Reserved.

PC87591L Datasheet(PDF) 329 Page - National Semiconductor (TI)

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