GC2011A datasheet(41/50 Pages) TI

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Texas Instruments Incorporated

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GC2011A 3.3V DIGITAL FILTER CHIP

SLWS129A

This document contains information which may be changed at any time without notice

6.10

NEW MODES REGISTER

This register controls the new modes added to the GC2011A chip. This address was not used in the GC2011

chip. Bits 8,9,12,13,14,and 15 power up low.

ADDRESS 12:

NEW_MODES

BIT

TYPE

NAME

DESCRIPTION

0-7 (LSBs)

R only

REVISION

These bits read back the current mask revision number.

R/W

POWER_DOWN

Forces the chip to be in the static power down mode when set.

R/W

DISABLE_CLOCK_LOSS_DETECT

Turns off the clock loss detect circuit when set. This bit should be kept

low.

10,11

R only

POWER_DOWN_STATUS

These bits go low when the chip is in the power down state,

either because bit 8 (POWER_DOWN) above is set, or because

clock loss has been detected. These bits are normally high.

R/W

INV_MSB_AOUT

Inverts the MSB of the A-output when set.

R/W

INV_MSB_BOUT

Inverts the MSB of the B-output when set.

R/W

INV_MSB_AIN

Inverts the MSB of the A-input when set.

15 (MSB)

R/W

INV_MSB_BIN

Inverts the MSB of the B-input when set.

The REVISION field can be used to determine the mask revision number for the GC2011A. The mask revision

numbers and the mask change descriptions are shown in Table 15 below (the mask codes are printed on the GC2011A

package).

The INV_MSB control bits will invert the MSB of the A and B inputs or the A and B outputs in order to convert

to and from offset binary and two’s complement formats. If the input data is offset binary, then the INV_MSB_AIN and/or

INV_MSB_BIN control bits should be set. If the output data needs to be converted to offset binary, then the

INV_MSB_AOUT and/or INV_MSB_BOUT control bits should be set.

Table 15: Mask Revisions

Mask

Revision

Number

(bits 0-7)

Release Date

Mask Code

on Package

Description

February 1999

55585B

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