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GC2011A Datasheet(PDF) 26 Page - Texas Instruments

Part # GC2011A
Description  3.3V DIGITAL FILTER CHIP
PDF  50 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

GC2011A Datasheet(HTML) 26 Page - Texas Instruments

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Texas Instruments Incorporated
- 22 -
GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
This document contains information which may be changed at any time without notice
3.10
DIAGNOSTICS
The user can use the ramp input and the snapshot memory to perform diagnostics on the chip. The suggested
diagnostic procedure is to configure the chip as it will be used in normal operation, but to select the ramp as the data
input source (see Section 6.1), to set the counter control to 0FFF HEX (see Section 6.4), and to set the snapshot controls
to capture 128 output samples (see Section 6.7). The snapshot should be triggered on TC with a delay of 4 blocks from
trigger. The delay guarantees that the filter has flushed and settled out before the snapshot is taken. The user can then
read the snapshot from memory and compare it against a known snapshot or save it for future comparison.
Two suggested diagnostic configurations are given below along with the expected snapshot output. These
configurations use all of the coefficient registers and all of the forward and reverse delay storage registers. The
diagnostic procedure is, for each test configuration in table 11:
(1)
Load the 11 control registers with the values shown in Table 11.
(2)
Load the coefficients h(k) in addresses 128+k for k=0 to 127.
(3)
Set the start bit in the snapshot register by writing 0413HEX to address 10.
(4)
Wait, while reading address 10, until the register value is 0463HEX.
(5)
Read addresses 256 through 271 and 384 through 399 and compare them to the expected values in
Table 12
.
Table 11: Diagnostic Test Configuration
Parameter
Address
Test A
Test B
h(k)
k modulo 4 = 0
EAAA
1555
k modulo 4 = 1
FFFF
E000
k modulo 4 = 2
0F0F
F0F0
k modulo 4 = 3
0001
1FFF
A_PATH_REG0
0
C402
E402
A_PATH_REG1
1
0292
0108
B_PATH_REG0
2
D402
E402
B_PATH_REG1
3
0214
02F2
CASCADE
4
1000
2F00
COUNTER
5
0FFF
0FFF
GAIN
6
1035
103A
OUTPUT
7
0041
0041
SNAP_REGA
8
004E
004F
SNAP_REGB
9
004F
005F
SNAP_REGC
10
0403
0403
NEW_MODES
12
0000
0000
Table 12: Expected Test Results
Address
Test A
Test B
Address
Test A
Test B
Address
Test A
Test B
Address
Test A
Test B
256
C302
A635
264
C621
C3D3
384
3BC2
4BAD
392
3CC2
4A33
257
C2E2
A606
265
CA1F
C8BD
385
3BE2
4B7E
393
3CE2
4A04
258
C2C2
A5D7
266
CE1E
CDA6
386
3C02
4B4F
394
3D02
49D4
259
C2A2
A5A8
267
D21D
D290
387
3C22
4B1F
395
3D22
49A5
260
C282
A578
268
D61B
F692
388
3C42
4AF0
396
3D41
4976
261
C262
A549
269
DA1A
0094
389
3C62
4AC1
397
3D61
4947
262
C243
A51A
270
DE19
0A97
390
3C82
4A91
398
3D81
4917
263
C223
A4EA
271
E217
1499
391
3CA2
4A62
399
3DA1
48E8



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