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GC2011A Datasheet(PDF) 25 Page - Texas Instruments |
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GC2011A Datasheet(HTML) 25 Page - Texas Instruments |
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25 / 50 page ![]() Texas Instruments Incorporated - 21 - GC2011A 3.3V DIGITAL FILTER CHIP SLWS129A This document contains information which may be changed at any time without notice 3.9 COMPLEX TO REAL QUADRATURE UPCONVERT Complex data can be converted to real data by doubling the sample rate, mixing the data up by FS/4 and saving the real part. The control settings for this mode are shown in Table 9. The filter is an interpolate by two low pass filter with a pass band from 0 to FS/4 and a stop band from FS/4 to FS/2, where FS is the output sample rate. The even coefficients of the filter are stored in the A-path filter cells and the odd-coefficients are stored in the B-path filter cells. The real half of the complex samples are input as A-in, and the imaginary half are input as B-in. The real results are output as A-out in all modes except for the double rate output mode. In the double rate output mode the even time samples are output as A-out and the odd time samples are output as B-out. In the full rate in to double rate out mode the coefficients h(k) are stored in register 1 of each filter cell. In this mode store h(k) in addresses: 128+2*k+1 for k even, and 192+2*k-1 for k odd, where k ranges from 0 to 31. h(31) is the center tap. In the half rate in to full rate out mode the coefficients are stored in registers 0 and 1 of each filter cell. In this mode store h(k) in addresses: 128+k for k modulo 4 = 0 192+k-1 for k modulo 4 = 1 128+k-1 for k modulo 4 = 2 192+k-2 for k modulo 4 = 3 where k ranges from 0 to 63. h(63) is the center tap. In the quarter rate in to half rate out mode the coefficients are stored in registers 0, 1, 2 and 3 of each filter cell. In this mode store h(k) in addresses: 128+k/2 for k even 192+(k-1)/2 for k odd where k ranges from 0 to 127. h(127) is the center tap. Table 10: Complex To Real Conversion Mode Control Register Settings I/O Rates Symmetr y # of Taps (N) A-PATH B-PATH Cascade Output Latency In Out REG0 REG1 REG0 REG1 REG REG Full Double Odd 63 20D8 6108 00D8 6181 2000 0001 44 Half Full 127 638B A218 438B A294 2000 0012 46 Quar- ter Half 255 A202 9018 8202 9094 2000 0033 50 |
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