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GC2011A Datasheet(PDF) 35 Page - Texas Instruments

Part # GC2011A
Description  3.3V DIGITAL FILTER CHIP
PDF  50 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

GC2011A Datasheet(HTML) 35 Page - Texas Instruments

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Texas Instruments Incorporated
- 31 -
GC2011A 3.3V DIGITAL FILTER CHIP
SLWS129A
This document contains information which may be changed at any time without notice
6.2
A-PATH AND B-PATH CONTROL REGISTER 1
Control registers APATH_REG1 and BPATH_REG1 are identical and are described here.
ADDRESS 1:
APATH_REG1
ADDRESS 3:
BPATH_REG1
BIT
TYPE
NAME
DESCRIPTION
0-4 (LSBs)
R/W
FEED_BACK
This 5 bit field controls the symmetric filter feedback mode according to the
following table:
FEED_BACK
DESCRIPTION
(HEX)
00
no symmetry
01
full rate odd symmetry
08
full rate even symmetry and
A-path cascade mode
11
decimate and interpolate by 2 odd symmetry
12
decimate by 2 even symmetry and
decimate by 4 odd symmetry
14
decimate by 4 even symmetry and
half and quarter rate odd symmetry
18
half and quarter rate even symmetry
NOTE: the A-path FEED_BACK control must be 08 in the
cascade mode.
5
R/W
ANTI_SYM
Anti-symmetric filters can be implemented by setting this bit and the CIN
bit described below. This bit complements (bitwise inverts) the feedback
data.
EXCEPTION: In the cascade mode the A-PATH ANTI_SYM bit must be
set for all filters.
6
R/W
CIN
This is the carry input to the filter cell’s 12 bit adder (See Figure 5). This
bit is set to create anti-symmetric filters. In the cascade mode this bit is
cleared in both paths to create a symmetric filter and it is set in both paths
to create an anti-symmetric filter.
7
R/W
ODD_SYM
This bit must be set for odd-symmetry filters and cleared for even
or non symmetric filters.
8-12
R/W
REV_DELAY
These five bits control the filter cells’ reverse delays.
These bits are not used if FEED_BACK=00 (no symmetry)
REV_DELAY
DESCRIPTION
(HEX)
00
no symmetry
01
full rate filters
02
decimate by 4 and half rate filters
0E
decimate and integrate by 2 filters
10
quarter rate filters
13-15(MSB)
R/W
FOR_DELAY
These 3 bits control the filter cells’ forward delays.
FOR_DELAY
DESCRIPTION
0
decimate and interpolate by 4 filters
1
decimate and interpolate by 2 filters
3
full rate filters
4
quarter rate filters
5
half rate filters



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