GC2011A datasheet(19/50 Pages) TI

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Texas Instruments Incorporated

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GC2011A 3.3V DIGITAL FILTER CHIP

SLWS129A

This document contains information which may be changed at any time without notice

3.2

HALF RATE

The number of taps in the filter can be doubled if the data rate into and out of the chip is one half the clock rate.

In this mode each filter cell stores two filter coefficients and performs two tap multiplications per output sample. The

cells’ delay lines are adjusted so that two feed-forward and two feedback data samples are delayed within each filter

cell. The accumulator at the end of the filter path sums the products to give the half rate output. The chip is configured

in the half rate mode using the control settings shown in Table 3.

The coefficients can be stored in coefficient registers 0 and 1 in each filter cell or registers 2 and 3. To store

coefficients h(k) in registers 0 and 1 of each filter cell use memory addresses:

BASE+2*k

for k even and

BASE+2*k-1

for k odd.

To use registers 2 and 3 store the coefficients in addresses

BASE+2*k+2

for k even and

BASE+2*k+1

for k odd.

Where BASE is 128 for A-path or cascaded filters, and is 192 for B-path filters.

To switch from using registers 0 and 1 to registers 2 and 3 add 0020HEX to the REG0 values shown in Table

3. Register switching is synchronized by the chip to the clock in order to prevent unwanted transients.

Table 3: Half Rate Mode Control Register Settings

Symmetry

Dual Path or

Cascaded

# of Taps

(N)

A-PATH

B-PATH

Cascade

Latency

REG0

REG1

REG0

REG1

REG

None

Dual

638B

AE00

438B

AE00

2000

Cascaded

638B

AE28

438B

AE00

5E00

Even

Dual

638B

A218

438B

A218

2000

Cascaded

128

638B

A228

438B

A218

5E00

Odd

Dual

638B

A294

438B

A294

2000

Cascaded

127

638B

A2A8

438B

A294

5E00

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