GC2011A datasheet(10/50 Pages) TI

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Texas Instruments Incorporated

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GC2011A 3.3V DIGITAL FILTER CHIP

SLWS129A

This document contains information which may be changed at any time without notice

2.2

CONTROL INTERFACE

The control interface performs five major functions: It allows an external processor to configure the chip, it

allows an external processor to load the filter coefficients, it allows an external processor to capture and read samples

from the chip, it allows an external processor to perform diagnostics, and it generates a one-shot synchronization strobe.

The chip is configured by writing control information into 16 bit control registers within the chip. The contents

of these control registers and how to use them are described in Section 6. The registers are written to or read from using

the C[0:15], A[0:8], CE, RE and WE pins. Each control register has been assigned a unique address within the chip.

This interface is designed to allow the GC2011A to appear to an external processor as a memory mapped peripheral

(the pin RE is equivalent to a memory chip’s OE pin).

The chip’s control address space is divided into thirteen control registers, 128 coefficient registers, and 256

snapshot memory words. The thirteen control registers are APATH_REG0, APATH_REG1, BPATH_REG0,

BPATH_REG1,

CASCADE_REG,

COUNTER_REG,

OUTPUT_REG,

SNAP_REGA,

SNAP_REGB,

SNAP_START_REG,ONE_SHOT, and NEW_MODES. The control registers are mapped to addresses 0 to 12. See

Section 6.0 for details about the contents of these registers.

The 128 filter coefficients are stored in 128 read/write registers which are accessed using addresses 128

through 255. There are 4 filter coefficients stored per filter cell. Addresses 128+4K, 128+4K+1, 128+4K+2 and

128+4K+3 are the four coefficient registers for filter cell K, where K ranges from 0 to 31. Filter cells 0 to 15 are in path-A

and filter cells 16 to 31 are in path-B.

The contents of the snapshot memory are accessed using addresses 256 through 511.

Address 11 is used to generate a one-shot pulse. This pulse, OS, which is one clock cycle wide, can be output

from the chip on the SO pin.

An external processor (a microprocessor, computer, or DSP chip) can write into a register by setting A[0:8] to

the desired register address, selecting the chip using the CE pin, setting C[0:15] to the desired value and then pulsing

WE low. The data will be written into the selected register when both WE and CE are low and will be held when either

signal goes high.

To read from a control register the processor must set A[0:8] to the desired address, select the chip with the

CE pin, and then set RE low. The chip will then drive C[0:15] with the contents of the selected register. After the

processor has read the value from C[0:15] it should set RE and CE high. The C[0:15] pins are turned off (high

impedance) whenever CE or RE are high or when WE is low. The chip will only drive these pins when both CE and RE

are low and WE is high.

One can also ground the RE pin and use the WE pin as a read/write direction control and use the CE pin as a

control I/O strobe. This mode is equivalent to the GC2011 control interface.

Figure 3 shows timing diagrams illustrating both I/O modes.

GC2011A Datasheet(PDF) 10 Page - Texas Instruments

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