GC2011A datasheet(15/50 Pages) TI

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Texas Instruments Incorporated

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GC2011A 3.3V DIGITAL FILTER CHIP

SLWS129A

This document contains information which may be changed at any time without notice

2.11

OUTPUT NEGATION

The output negation control allows every other output sample to be negated. This is used to mix complex data

up in frequency by a quarter or half of the output sample rate. This is used primarily when converting complex data to

real.

2.12

GAIN

The gain of the filter can be adjusted in 0.5 dB steps using the gain circuit. The 32 bit sum output is multiplied

by the gain value 2S(1+F/16) where S and F range from 0 to 15. The result is saturated to plus or minus full scale

whenever the product overflows the 32 bit word. The AOF and BOF output bits pulse high for one clock cycle each time

an overflow is detected. The output is then rounded to the upper 8, 10, 12, 16, 20 or 24 bits of the result. The lower bits

are cleared.

The gain adjustment allows the user to scale the filter coefficients in order to optimize the filter’s dynamic range,

and then to readjust the overall filter gain using the gain circuit.

2.13

OUTPUT MUX

The output multiplexor circuit formats the gain outputs for output from the chip. In the dual path mode the upper

16 bit of each gain output word are passed to the A-out and B-out pins. If the output data rate is half or quarter rate, then

the user can have the A-path and B-path outputs multiplexed onto the A-out pins.

In the cascade or 24 bit modes the B path result can be output as a 24 bit value using a combination of the

A-out and B-out pins. In the 24 bit output mode the upper 16 bits are output on the A-out pins and the lower 8 bits are

output on the upper 8 B-out pins.

2.14

SNAPSHOT MEMORY

The snapshot memory is used to capture blocks of input or output samples. The memory can be configured

as two independent snapshots, or one longer snapshot. In the dual mode the memory can be configured to capture two

128 word by 16 bit snapshots, or two 256 byte by 8 bit snapshots. In the single mode the memory can be configured to

capture a 256 word by 16 bit snapshot, or a 512 byte by 8 bit snapshot.

The snapshot data can come from the A-in, B-in, A-out, or B-out samples. In the dual mode the input selection

for the two memories can be made independently. In the 8 bit mode the upper 8 bits of each data source is stored in

the snapshot. In the 16 bit mode the 12 bit A-in or B-in samples are stored in the upper 12 bits of the 16 bit snapshot.

The snapshot can be programmed to store every sample, every-other sample, every third sample, or every

forth sample. This is useful when the chip’s input or output data rate is less than the clock rate.

The snapshot is started by writing configuration information to control registers SNAP_REGA, SNAP_REGB

and SNAP_REGC, and then setting the START bit in SNAP_REGC (See Section 6.8). The snapshot then waits for a

trigger condition plus an optional delay before starting. The trigger conditions are: start immediately after START is set,

trigger on the snapshot sync (SN) strobe, trigger on the sync input (SI) strobe, or trigger on the counter’s (see Section

2.3) terminal count (TC) strobe. The delay from trigger can be set to multiples of 128 sample times, where the sample

time depends upon the selected data rate. The delay is 128DR, where D is the delay count ranging from 0 to 15 and R

is the rate ranging from 1 to 4. The delay setting is useful when there are multiple GC2011A chips running in parallel

and the user wishes to capture a longer snapshot. For example, a two chip configuration could capture 1024 samples

by setting up one chip to capture samples 0 to 511 and setting up the second chip with a delay setting of 512 to capture

512 samples.

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