GC2011A datasheet(24/50 Pages) TI

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Texas Instruments Incorporated

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GC2011A 3.3V DIGITAL FILTER CHIP

SLWS129A

This document contains information which may be changed at any time without notice

3.8

REAL TO COMPLEX QUADRATURE DOWN CONVERT

The chip can convert from real data to complex data by mixing the data down by FS/4, low pass filtering the

result and then decimating by a factor of two. The control register settings for this mode are shown in Table 9. The

double rate input mode assumes the even time samples are in the A-path inputs and the odd time samples are the

B-path inputs. The real output is the A-out and the imaginary output is the B-out.

The low pass filter coefficients h(k) are stored so that the even coefficients are stored in the A-path filter cells

and the odd coefficients are stored in the B-path filter cells. The lowpass filter should be designed to cut off frequencies

above FS/4 for the double to full, full to half, or half to quarter modes, where FS is the input sample rate. The cut off

frequencies are FS/8 and FS/16 for the double to half and double to quarter modes, respectfully.

In the double rate in to full rate out mode the coefficients are stored in register 1 of each filter cell. In this mode

store h(k) in addresses:

128+2*k+1

for k even, and

192+2*k-1

for k odd,

where k ranges from 0 to 31. h(31) is the center tap.

In the double or full rate in to half rate out modes the coefficients are stored in registers 0 and 1 of each filter

cell. In this mode store h(k) in addresses:

128+k

for k modulo 4 = 0

192+k-1

for k modulo 4 = 1

128+k-1

for k modulo 4 = 2

192+k-2

for k modulo 4 = 3

where k ranges from 0 to 63. h(63) is the center tap.

In the double or half rate in to quarter rate out modes the coefficients are stored in registers 0, 1, 2 and 3 of

each filter cell. In this mode store h(k) in addresses:

128+k/2

for k even

192+(k-1)/2

for k odd

where k ranges from 0 to 127. h(127) is the center tap.

Table 9: Real To Complex Conversion Mode Control Register Settings

I/O Rates

Symmetr

# of Taps

(N)

A-PATH

B-PATH

Cascade

Latency

Out

REG0 REG1 REG0 REG1

REG

Double

Full

Odd

24D8

6108

04D8

6181

2000

Half

127

248B

2E12

048B

2E91

2000

Quarter

255

2402

0214

0402

0292

2000

Full

Half

127

6B8B

A218

2B8B

A294

2000

Half

Quarter

255

AE02

9018

6E02

9094

2000

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