GC2011A datasheet(33/50 Pages) TI

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Texas Instruments Incorporated

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GC2011A 3.3V DIGITAL FILTER CHIP

SLWS129A

This document contains information which may be changed at any time without notice

6.1

A-PATH AND B-PATH CONTROL REGISTER 0

Control registers APATH_REG0 and BPATH_REG0 are identical and are described here.

ADDRESS 0:

APATH_REG0

ADDRESS 2:

BPATH_REG0

BIT

TYPE

NAME

DESCRIPTION

0,1 (LSBs)

R/W

ACCUM

This two bit field controls the accumulator according to the

following table:

ACCUM

DESCRIPTION

0,1

don’t accumulate (full rate output)

accumulate 4 sums (quarter rate)

accumulate 2 sums (half rate)

The ACCUM control also sets the output data rate as shown in

Figure 8.

R/W

UNSIGNED

The filter cell adder (See Figure 5) is in the unsigned mode when

this bit is set.

3-7

R/W

COEF_SEL

This five bit field controls how the four coefficients are used

within the filter cells. The controls are:

COEF_SEL

DESCRIPTION

(HEX)

use coefficient reg 1

use coefficient reg 3

toggle between registers 0 and 1

toggle between registers 2 and 3

cycle through all four registers

8,9

R/W

RATE

This two bit field sets the input rate as follows: (See Figure 7)

RATE

DESCRIPTION

0,1

full rate input

quarter rate input

half rate input

10-12

R/W

NEG_IN

These three bits control the input sample negation as follows:

NEG_IN

DESCRIPTION

don’t negate

negate even time full rate samples

negate odd time half rate samples

negate even time quarter rate samples

always negate

negate odd time full rate samples

negate even time half rate samples

negate odd time quarter rate samples

where the definition of even and odd time samples is shown in

Figure 7.

R/W

AB_SEL

Select input A-in when high, B-in when low.

14,15(MSB)

R/W

DELAY_SEL

Selects the input delay or counter input as follows:

DELAY_SEL

DESCRIPTION

no delay

one clock delay

3 clock delay

use counter as input

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