GC2011A datasheet(46/50 Pages) TI

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Texas Instruments Incorporated

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GC2011A 3.3V DIGITAL FILTER CHIP

SLWS129A

This document contains information which may be changed at any time without notice

8.5

SYNCHRONIZING MULTIPLE GC2011A CHIPS

A system containing a bank of GC2011A chips will need to be synchronized so that the output data from each

chip are aligned. This is especially important for the half rate and quarter rate I/O modes. The synchronization can be

achieved by connecting the SI inputs of all the chips to a system sync input. If a system sync is not available, then the

counter within the GC2011A chip can be used to generate one. The TC strobe of the counter can be output from a

“master” GC2011A and used as the SI input for all other GC2011A chips. The SO should also be used as the SN (snap

strobe) input to all of the chip, including the master chip, so that the snapshot memories within all of the chips can be

synchronized.

For example, two chips can be operated in parallel as a complex filter processing complex data. The suggested

configuration for these chips is shown in Figure 9.

Figure 9. Processing Complex Input Data

In this configuration the slave chip generates the I-outputs and the master chip generates the Q-outputs. The

two chips are synchronized by connecting the SO signal from the master chip to the SN inputs of both chips and to the

SI input of the slave chip. A system sync, if available, can be used to synchronize the master chip to the rest of the

system. If a system sync is not available, then a one shot strobe generated by the slave chip and output on the SO pin,

can be routed into the SI input of the master chip. This is shown as the dashed line in Figure 9. The SO from the master

chip can then be used as a system sync for the rest of the system.

GC2011A

IOUT

QOUT

IIN

QIN

SYNC

SYNC OUT

“Master”

“Slave”

GC2011A Datasheet(PDF) 46 Page - Texas Instruments