GC2011A datasheet(37/50 Pages) TI

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Texas Instruments Incorporated

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GC2011A 3.3V DIGITAL FILTER CHIP

SLWS129A

This document contains information which may be changed at any time without notice

ADDRESS 6:

GAIN_REG

BIT

TYPE

NAME

DESCRIPTION

0-3

R/W

The 4 bit gain fraction.

4-7

R/W

The 4 bit gain exponent.

8-14

R/W

ROUND

Controls the output rounding according to the following table:

ROUND

DESCRIPTION

(HEX)

Truncate

Round to the 8 MSBs

Round to the 10 MSBs

Round to the 12 MSBs

Round to the 14 MSBs

Round to the 16 MSBs

Round to the 20 MSBs

Round to the 24 MSBs

15 (MSB)

R/W

Unused

The chip’s output gain is set using F and S according to the following formula:

GAIN =2(S-20)(1+F/16)(DC_GAIN)

Where DC_GAIN is the sum of the filter coefficients. Unity gain, according to this formula, will map the MSB of the12 bit

input data (AI11 or BI11) into the MSB of the selected output word (AO15 or BO15).

The 32 bit filter path output is rounded to the number of most significant bits selected by the round control. The

gain circuit output is saturated to plus or minus full scale if the GAIN setting causes an overflow. The AOF or BOF output

pins will go high whenever an overflow is detected in the A-Path or B-path gain circuit.

For example: If the DC gain of the filter coefficients is 215 (i.e., the sum of the coefficients is 215), then the

overall gain of the filter can be set to unity by setting S to 5 and F to 0.

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