MCP19124 datasheet(107/236 Pages) MICROCHIP

107 / 236 page

 2016 Microchip Technology Inc.

DS20005619A-page 107

MCP19124/5

17.0 I/O PORTS

In general, when a peripheral is enabled, that pin may

not be used as a general-purpose I/O pin.

Each port has the registers for its operation. These

registers are:

• TRISGPx registers (data direction register)

• PORTGPx registers (read the levels on the pins of

the device)

Some ports may have one or more of the following

additional registers. These registers are:

• ANSELx (analog select)

• WPUGPx (weak pull-up)

Ports with analog functions also have an ANSELx

power. A simplified model of a generic I/O port, without

the interfaces to other peripherals, is shown in

Figure 17-1.

FIGURE 17-1:

GENERIC I/O PORTGPX

OPERATION

EXAMPLE 17-1:

INITIALIZING PORTGPA

17.1

PORTGPA and TRISGPA Registers

PORTGPA is an 8-bit wide, bidirectional port consisting

of five CMOS I/Os, one open-drain I/O and one

open-drain input-only pin (GPA4 is not available). The

corresponding data direction register is TRISGPA.

Setting a TRISGPA bit to ‘1’ will make the

corresponding PORTGPA pin an input (i.e., disable the

output driver). Clearing a TRISGPA bit set to ‘0’ will

make the corresponding PORTGPA pin an output (i.e.,

enables output driver). The exception is GPA5, which is

input only and its TRISGPA bit will always read as ‘1’.

Example 17-1 shows how to initialize an I/O port.

Reading the PORTGPA register reads the status of the

pins, whereas writing to it will write to the PORT latch.

All write operations are read-modify-write operations.

The TRISGPA register controls the PORTGPA pin

output drivers, even when they are being used as

analog inputs. The user must ensure the bits in the

TRISGPA register are maintained set when using them

as analog inputs. I/O pins configured as analog input

always read ‘0’. If the pin is configured for a digital

output (either port or alternate function), the TRISGPA

bit must be cleared in order for the pin to drive the

signal, and a read will reflect the state of the pin.

17.1.1

INTERRUPT-ON-CHANGE

Each PORTGPA pin is individually configurable as an

interrupt-on-change pin. Control bits IOCB<7:4> and

IOCB<2:0> enable or disable the interrupt function for

each pin. The interrupt-on-change feature is disabled

on a Power-On Reset. Reference Section 18.0

“Interrupt-On-Change” for more information.

17.1.2

WEAK PULL-UPS

PORTGPA <3:0> and PORTGPA5 have an internal weak

pull-up. PORTGPA<7:6> do not have internal weak

pull-ups. Individual control bits can enable or disable the

internal weak pull-ups (refer to Register 17-3). The weak

pull-up is automatically turned off when the port pin is

configured as an output, an alternative function or on a

Power-On Reset setting the RAPU bit in the

OPTION_REG register. The weak pull-up on GPA5 is

enabled when configured as MCLR pin by setting bit 5 in

the CONFIG register, and disabled when GPA5 is an I/O.

There is no software control of the MCLR pull-up.

Write LATx

Data Register

Read PORTGPx

Write PORTGPx

TRISGPx

Read LATx

Data Bus

To peripherals

ANSELx

VDD

AGND

I/O pin

; This code example illustrates

; initializing the PORTGPA register. The

; other ports are initialized in the same

; manner.

BANKSEL PORTGPA;

CLRF

PORTGPA;Init PORTA

BANKSEL ANSELA;

CLRF

ANSELA;digital I/O

BANKSEL TRISGPA;

MOVLW

B'00011111';Set GPA<3:0> as

;inputs

MOVWF

TRISGPA;and set GPA<7:5> as

;outputs

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