MCP19124 datasheet(111/236 Pages) MICROCHIP

111 / 236 page

 2016 Microchip Technology Inc.

DS20005619A-page 111

MCP19124/5

17.2

PORTGPB and TRISGPB

Registers

Due to special function pin requirements, a limited

number of the PORTGPB I/Os are utilized. On the

24-pin 4x4 mm QFN MCP19124, GPB0 and GPB1 are

implemented. GPB0 is an open-drain general-purpose

I/O and SDA pin. GPB1 is a general-purpose I/O,

analog input and VREF2 DAC output. The 28-pin

5x5 mm QFN

MCP19124

has

four

additional

general-purpose

PORTGPB

I/O

pins.

The

corresponding data direction register is TRISGPB.

Setting a TRISGPB bit to ‘1’ will make the

corresponding PORTGPB pin an input (i.e., disable the

output driver). Clearing a TRISGPB bit to ‘0’ will make

the corresponding PORTGPB pin an output (i.e.,

enable the output driver). Example 17-1 shows how to

initialize an I/O port.

Some pins for PORTGPB are multiplexed with an

alternate function for the peripheral or a clock function.

In general, when a peripheral or clock function is

enabled,

that

may

not

used

general-purpose I/O pin.

Reading the PORTGPB register reads the status of the

pins, whereas writing to it will write to the PORT latch.

All write operations are read-modify-write operations.

The TRISGPB register controls the PORTGPB pin out-

put drivers, even when they are being used as analog

inputs. The user should ensure the bits in the TRISGPB

inputs. I/O pins configured as analog input always read

‘0’. If the pin is configured for a digital output (either port

or alternate function), the TRISGPB bit must be cleared

in order for the pin to drive the signal and a read will

reflect the state of the pin.

17.2.1

INTERRUPT-ON-CHANGE

Each PORTGPB pin is individually configurable as an

interrupt-on-change pin. Control bits IOCB<7:4> and

IOCB<2:0> enable or disable the interrupt function for

each pin. The interrupt-on-change feature is disabled

on a Power-On Reset. Reference Section 18.0

“Interrupt-On-Change” for more information.

17.2.2

WEAK PULL-UPS

Each of the PORTGPB pins has an individually

configurable internal weak pull-up. Control bits

WPUB<7:4> and WPUB1 enable or disable each

pull-up (refer to Register 17-7). Each weak pull-up is

automatically turned off when the port pin is configured

as an output. All pull-ups are disabled on a

Power-On Reset by the RAPU bit in the OPTION_REG

17.2.3

ANSELB REGISTER

The ANSELB register is used to configure the input

mode of an I/O pin to analog. Setting the appropriate

ANSELB bit high will cause all digital reads on the pin

to be read as ‘0’ and allow analog functions on the pin

to operate correctly.

The state of the ANSELB bits has no effect on the digital

output functions. A pin with TRISGPB clear and

ANSELB set will still operate as a digital output, but the

input mode will be analog. This can cause unexpected

behavior when executing read-modify-write instructions

on the affected port.

The TRISGPB register controls the PORTGPB pin output

drivers, even when they are being used as analog inputs.

The user should ensure the bits in the TRISGPB register

are maintained set when using them as analog inputs. I/O

pins configured as analog input always read ‘0’.

TABLE 17-2:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTGPA

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on Page

ANSELA

—

ANSA3

ANSA2

ANSA1

ANSA0

110

OPTION_REG

RAPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

PORTGPA

GPA7

GPA6

GPA5

—

GPA3

GPA2

GPA1

GPA0

109

TRISGPA

TRISA7

TRISA6

TRISA5

—

TRISA3

TRISA2

TRISA1

TRISA0

109

WPUGPA

—

WPUA5

—

WPUA3

WPUA2

WPUA1

WPUA0

110

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by PORTGPA.

Note:

The ANSELB bits default to the Analog

mode after Reset. To use any pins as

digital general-purpose or peripheral

inputs, the corresponding ANSELB bits

must be initialized to ‘0’ by the user’s

software.

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