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MCP19124 Datasheet(PDF) 115 Page - Microchip Technology

Part # MCP19124
Description  Digitally-Enhanced Power Analog Synchronous Low-Side Dual-Loop PWM Controller
PDF  236 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP19124 Datasheet(HTML) 115 Page - Microchip Technology

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 2016 Microchip Technology Inc.
DS20005619A-page 115
MCP19124/5
18.0 INTERRUPT-ON-CHANGE
Each PORTGPA and PORTGPB pin is individually
configurable as an interrupt-on-change pin. Control bits
IOCA and IOCB enable or disable the interrupt function
for each pin. Refer to Registers 18-1 and 18-2. The
interrupt-on-change is disabled on a Power-On Reset.
The interrupt-on-change on GPA5 is disabled when
configured as MCLR pin in the CONFIG register.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTGPA or PORTGPB. The mismatched outputs of
the last read of all the PORTGPA and PORTGPB pins
are OR’d together to set the Interrupt-on-Change
Interrupt Flag (IOCF) bit in the INTCON register.
18.1
Enabling the Module
To allow individual port pins to generate an interrupt, the
IOCE bit in the INTCON register must be set. If the IOCE
bit is disabled, the edge detection on the pin will still
occur, but an interrupt will not be generated.
18.2
Individual Pin Configuration
To enable a pin to detect an interrupt-on-change, the
associated IOCAx or IOCBx bit in the IOCA or IOCB
registers is set.
18.3
Clearing Interrupt Flags
The user, in the Interrupt Service Routine, clears the
interrupt by:
a) Any read of PORTGPA or PORTGPB AND
Clear flag bit IOCF. This will end the mismatch
condition.
OR
b) Any write of PORTGPA or PORTGPB AND
Clear flag bit IOCF will end the mismatch
condition.
A mismatch condition will continue to set flag bit IOCF.
Reading PORTGPA or PORTGPB will end the
mismatch condition and allow flag bit IOCF to be
cleared. The latch holding the last read value is not
affected by a MCLR Reset. After this Reset, the IOCF
flag will continue to be set if a mismatch is present.
18.4
Operation in Sleep
The interrupt-on-change interrupt sequence will wake
the device from Sleep mode, if the IOCE bit is set.
Note:
If a change on the I/O pin should occur
when any PORTGPA or PORTGPB
operation is being executed, the IOCF
interrupt flag may not get set.



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