MCP19124 datasheet(131/236 Pages) MICROCHIP

131 / 236 page

 2016 Microchip Technology Inc.

DS20005619A-page 131

MCP19124/5

20.0 FLASH PROGRAM MEMORY

CONTROL

The Flash program memory is readable and writable

during normal operation (full VIN range). This memory is

not directly mapped in the register file space. Instead, it

is indirectly addressed through the Special Function

Registers (refer to Registers 20-1 to 20-5). There are

six SFRs used to read and write this memory:

•PMCON1

•PMCON2

•PMDATL

•PMDATH

•PMADRL

•PMADRH

When interfacing the program memory block, the

PMDATL and PMDATH registers form a two-byte

word, which holds the 14-bit data for read/write, and

the PMADRL and PMADRH registers form a two-byte

word, which holds the 13-bit address of the FLASH

location being accessed. These devices have

8k words of program Flash with an address range from

0000h to 1FFFh.

The program memory allows single-word read and a

four-word write. A four-word write automatically erases

the row of the location and writes the new data (erase

before write).

The write time is controlled by an on-chip timer. The

write/erase voltages are generated by an on-chip

charge pump rated to operate over the voltage range

of the device for byte or word operations.

When the device is code-protected, the CPU may

continue to read and write the Flash program memory.

Depending on the settings of the Flash Program

Memory Enable (WRT<1:0>) bits, the device may or

may not be able to write certain blocks of the program

memory; however, reads of the program memory are

allowed.

When the Flash Program Memory Code Protection

(CP) bit is enabled, the program memory is

code-protected and the device programmer (ICSP)

cannot access data or program memory.

20.1

PMADRH and PMADRL Registers

The PMADRH and PMADRL registers can address up

to a maximum of 8k words of program memory.

When selecting a program address value, the Most

Significant Byte (MSB) of the address is written to the

PMADRH register and the Least Significant Byte

(LSB) is written to the PMADRL register.

20.2

PMCON1 and PMCON2 Registers

The PMCON1 register is the control register for the

data program memory accesses.

Control bits RD and WR initiate read and write,

respectively. In software, these bits can only be set,

not cleared. They are cleared in hardware at

completion of the read or write operation. The inability

to clear the WR bit in software prevents the accidental

premature termination of a write operation.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear.

The CALSEL bit allows the user to read locations in

test memory in case there are calibration bits stored in

the calibration word locations that need to be

transferred to SFR trim registers. The CALSEL bit is

only for reads. If a write operation is attempted with

CALSEL = 1, no write will occur.

PMCON2 is not a physical register. Reading PMCON2

will read all ‘0’s. The PMCON2 register is used

exclusively in the flash memory write sequence.

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