MCP19124 datasheet(146/236 Pages) MICROCHIP

146 / 236 page

MCP19124/5

DS20005619A-page 146

 2016 Microchip Technology Inc.

24.2

Compare Mode

In Compare mode, the 16-bit CCDRx register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the CMPx pin:

• Is driven high

• Is driven low

• Toggles

• Remains unchanged

The action on the pin is based on the value of the

control bits, CCxM3:CCxM0. At the same time,

interrupt flag bit, CCP1IF, is set.

FIGURE 24-2:

COMPARE MODE OPERATION BLOCK DIAGRAM

24.2.1

CMPX PIN CONFIGURATION

The user must configure the CMPx pin as an output by

clearing the TRIS bit for that pin.

24.2.2

TIMER1 MODE SELECTION

Timer1 must be running off of the instruction clock for

the CCD module to use the compare feature. If Timer1

is running off of the 8 MHz clock, the compare feature

may not function correctly.

24.2.3

SOFTWARE INTERRUPT MODE

When Generate Software Interrupt mode is chosen, the

CCP1 pin is not affected. The CCP1IF bit is set,

causing a CCx interrupt (if enabled).

24.2.4

SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated,

which may be used to initiate an action. The Special

Event Trigger output of CCD does not reset the TMR1

module is enabled).

Special Event

Trigger

Match

TRIS

Output Enable

CCDCON<CCxM3:0>

Mode Select

CCDRxH

CCDRxL

CCD pin

Set CCDxIF

Interrupt Flag

(PIR1)

Output

Logic

TMR1H

TMR1L

Comparator

Special Event Trigger will:

- NOT set interrupt flag bit TMR1IF in the PIR1 register.

- Set the GO/DONE bit to start the ADC conversion.

Note: Clearing the CCxM<3:0> bits will set the

CMPx compare output latch to the default

state. This is not the GPIO pin data latch.

The default state for set on match or toggle

on match is ‘0’ but the default state for clear

on match is ‘1’.

Note: The Special Event Trigger from the CCD

module will not set the interrupt flag bit

TMR1IF (bit 0 in the PIR1 register).

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