MCP19124 datasheet(158/236 Pages) MICROCHIP

158 / 236 page

MCP19124/5

DS20005619A-page 158

 2016 Microchip Technology Inc.

FIGURE 28-2:

MSSP BLOCK DIAGRAM

(I2C SLAVE MODE)

28.2

I2C

MODE OVERVIEW

The Inter-Integrated Circuit Bus (I2C) is a multi-master

serial data communication bus. Devices communicate

in a master/slave environment, where the master

devices initiate the communication. A slave device is

controlled through addressing.

The I2C bus specifies two signal connections:

• Serial Clock (SCL)

• Serial Data (SDA)

Both the SCL and SDA connections are bidirectional

open-drain lines, each requiring pull-up resistors for the

supply voltage. Pulling the line to ground is considered

a logical zero; letting the line float is considered a

logical one.

Figure 28-3 shows a typical connection between two

devices configured as master and slave.

The I2C bus can operate with one or more master

devices and one or more slave devices.

There are four potential modes of operation for a given

device:

• Master Transmit mode

(master is transmitting data to a slave)

• Master Receive mode

(master is receiving data from a slave)

• Slave Transmit mode

(slave is transmitting data to a master)

• Slave Receive mode

(slave is receiving data from a master)

To begin communication, a master device starts out in

Master Transmit mode. The master device sends out a

Start bit followed by the address byte of the slave it

intends to communicate with. This is followed by a

single Read/Write bit, which determines whether the

master intends to transmit to or receive data from the

slave device.

If the requested slave exists on the bus, it will respond

with an Acknowledge bit, otherwise known as an ACK.

The master then continues in either Transmit mode or

Receive mode and the slave continues in the

complement, either in Receive mode or Transmit

mode, respectively.

A Start bit is indicated by a high-to-low transition of the

SDA line while the SCL line is held high. Address and

data bytes are sent out Most Significant bit (MSb) first.

The Read/Write bit is sent out as a logical one when the

master intends to read data from the slave, and is sent

out as a logical zero when it intends to write data to the

slave.

FIGURE 28-3:

I2C MASTER/

SLAVE CONNECTION

The Acknowledge bit (ACK) is an active-low signal that

holds the SDA line low to indicate to the transmitter that

the slave device has received the transmitted data and

is ready to receive more.

The transition of a data bit is always performed while

the SCL line is held low. Transitions that occur while the

SCL line is held high are used to indicate Start and Stop

bits.

If the master intends to write to the slave, it repeatedly

sends out a byte of data, with the slave responding

after each byte with an ACK bit. In this example, the

master device is in Master Transmit mode and the

slave is in Slave Receive mode.

If the master intends to read from the slave, it

repeatedly receives a byte of data from the slave and

responds after each byte with an ACK bit. In this

example, the master device is in Master Receive mode

and the slave is Slave Transmit mode.

Read

Write

SSPSR Reg

Match Detect

SSPADD Reg

Start and

Stop bit Detect

SSPBUF Reg

Internal

Data Bus

Addr Match

Set, Reset

S, P bits

(SSPSTAT Reg)

SCL

SDA

Shift

Clock

MSb

LSb

SSPMSK1 Reg

Master

SCL

SDA

SCL

SDA

Slave

VDD

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