MCP19124 datasheet(162/236 Pages) MICROCHIP

162 / 236 page

MCP19124/5

DS20005619A-page 162

 2016 Microchip Technology Inc.

28.3.9

ACKNOWLEDGE SEQUENCE

The ninth SCL pulse for any transferred byte in I2C is

dedicated as an Acknowledge. It allows receiving

devices to respond back to the transmitter by pulling

the SDA line low. The transmitter must release control

of the line during this time to shift in the response. The

Acknowledge (ACK) is an active-low signal, pulling the

SDA line low, indicating to the transmitter that the

device has received the transmitted data and is ready

to receive more.

The result of an ACK is placed in the ACKSTAT bit in

the SSPCON2 register.

Slave software, when the AHEN and DHEN bits are

set, allows the user to set the ACK value sent back to

the transmitter. The ACKDT bit in the SSPCON2

Slave hardware will generate an ACK response if the

AHEN and DHEN bits in the SSPCON3 register are

clear.

There are certain conditions where an ACK will not be

sent by the slave. If the BF bit in the SSPSTAT register

or the SSPOV bit in the SSPCON1 register are set

when a byte is received, the ACK will not be sent.

When the module is addressed, after the 8th falling

edge of SCL on the bus, the ACKTIM bit in the

SSPCON3 register is set. The ACKTIM bit indicates

the acknowledge time of the active bus. The ACKTIM

status bit is only active when the AHEN or DHEN bits

are enabled.

28.4

I2C

SLAVE-MODE OPERATION

The MSSP Slave mode operates in one of the four

modes selected in the SSPM bits in SSPCON1

10-bit Addressing mode. 10-bit Addressing mode

operates the same as 7-bit, with some additional

overhead for handling the larger addresses.

Modes with Start and Stop bit interrupts operate the

same as the other modes, with SSPIF additionally getting

set upon detection of a Start, Restart or Stop condition.

28.4.1

SLAVE MODE ADDRESSES

The SSPADD register contains the Slave mode

address. The first byte received after a Start or Restart

condition is compared against the value stored in this

the SSPBUF register and an interrupt is generated. If

the value does not match, the module goes idle and no

indication is given to the software that anything

happened.

The SSPMSK1 register affects the address matching

process. Refer to Section 28.4.10 “SSPMSK1

28.4.2

SECOND SLAVE MODE ADDRESS

The SSPADD2 register contains a second 7-bit Slave

mode address. The first byte received after a Start or

Restart condition is compared against the value stored

in this register. If the byte matches, the value is loaded

into the SSPBUF register and an interrupt is

generated. If the value does not match, the module

goes idle and no indication is given to the software that

anything happened.

The SSPMSK2 register affects the address matching

process.

Refer to Section 28.4.10 “SSPMSK1

28.4.2.1

I2C Slave 7-Bit Addressing Mode

In 7-bit Addressing mode, the LSb of the received data

byte is ignored when determining if there is an address

match.

28.4.2.2

I2C Slave 10-Bit Addressing Mode

In 10-bit Addressing mode, the first received byte is

compared to the binary value of ‘1 1 1 1 0 A9 A8

’. A9 and A8 are the two MSb of the 10-bit address

and are stored in bits 2 and 1 in the SSPADD register.

After the high byte has been acknowledged, the UA bit

is set and SCL is held low until the user updates

SSPADD with the low address. The low address byte is

clocked in, and all 8 bits are compared to the low

address value in SSPADD. Even if there is no address

match, SSPIF and UA are set and SCL is held low until

SSPADD is updated to receive a high byte again. When

SSPADD is updated, the UA bit is cleared. This

ensures the module is ready to receive the high

address byte on the next communication.

A high and low address match as a write request is

required at the start of all 10-bit addressing

communication. A transmission can be initiated by

issuing a Restart once the slave is addressed, and

clocking in the high address with the R/W bit set. The

slave hardware will then acknowledge the read

request and prepare to clock out data. This is only

valid for a slave after it has received a complete high

and low address-byte match.

28.4.3

SLAVE RECEPTION

When the R/W bit of a matching received address byte

is clear, the R/W bit in the SSPSTAT register is cleared.

The received address is loaded into the SSPBUF

When an overflow condition exists for a received

address, then Not Acknowledge is given. An overflow

condition is defined as either bit BF in the SSPSTAT

set. The BOEN bit in the SSPCON3 register modifies this

operation. For more information, refer to Register 28-4.

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