MCP19124 datasheet(163/236 Pages) MICROCHIP

163 / 236 page

 2016 Microchip Technology Inc.

DS20005619A-page 163

MCP19124/5

An MSSP interrupt is generated for each transferred

data byte. Flag bit SSPIF must be cleared by software.

When the SEN bit in the SSPCON2 register is set, SCL

will be held low (clock stretch) following each received

byte. The clock must be released by setting the CKP

bit in the SSPCON1 register, except sometimes in

10-bit mode.

28.4.3.1

7-Bit Addressing Reception

This section describes a standard sequence of events

for the MSSP module configured as an I2C Slave in

7-bit Addressing mode, including all decisions made

by hardware or software and their effect on reception.

Figures 28-5 and 28-6 are used as a visual reference

for this description.

This is a step-by-step process of what typically must

be done to accomplish I2C communication:

Start bit is detected.

S bit in the SSPSTAT register is set; SSPIF is set

if interrupt on Start detect is enabled.

Matching address with R/W bit clear is received.

The slave pulls SDA low, sending an ACK to the

master, and sets SSPIF bit.

Software clears the SSPIF bit.

Software reads received address from SSPBUF

clearing the BF flag.

If SEN = 1, Slave software sets CKP bit to

release the SCL line.

The master clocks out a data byte.

Slave drives SDA low sending an ACK to the

master, and sets SSPIF bit.

10. Software clears SSPIF.

11. Software reads the received byte from SSPBUF

clearing BF.

12. Steps 8–12 are repeated for all received bytes

from the Master.

13. Master sends Stop condition, setting P bit in the

SSPSTAT register, and the bus goes idle.

28.4.3.2

7-Bit Reception with AHEN and

DHEN

Slave device reception with AHEN and DHEN set

operates the same as without these options with extra

interrupts and clock stretching added after the 8th falling

edge of SCL. These additional interrupts allow the slave

software to decide whether it wants the ACK to receive

address or data byte, rather than the hardware.

Figure 28-7 displays a module using both address and

data holding. Figure 28-8 includes the operation with

the SEN bit in the SSPCON2 register set. The

following list describes the steps that need to be taken

by slave software to use these options for I2C

communication:

S bit in the SSPSTAT register is set; SSPIF is set

if interrupt on Start detect is enabled.

Matching address with R/W bit clear is clocked

in. SSPIF is set and CKP cleared after the 8th

falling edge of SCL.

Slave clears the SSPIF.

Slave can look at the ACKTIM bit in the

SSPCON3 register to determine if the SSPIF

was after or before the ACK.

Slave reads the address value from SSPBUF,

clearing the BF flag.

Slave sets ACK value clocked out to the master

by setting ACKDT.

Slave releases the clock by setting CKP.

SSPxIF is set after an ACK, not after a NACK.

If SEN = 1 the slave hardware will stretch the

clock after the ACK.

10. Slave clears SSPIF.

11. SSPIF set and CKP cleared after 8th falling edge

of SCL for a received data byte.

12. Slave looks at ACKTIM bit in the SSPCON3

13. Slave reads the received data from SSPBUF

clearing BF.

14. Steps 7-14 are the same for each received data

byte.

15. Communication is ended by either the slave

sending an ACK = 1 or the master sending a

Stop condition. If a Stop is sent and Interrupt on

Stop Detect is disabled, the slave will only know

by polling the P bit in the SSPSTAT register.

Note: SSPIF is still set after the 9th falling edge of

SCL even if there is no clock stretching and

BF has been cleared. Only if NACK is sent

to Master is SSPIF not set.

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