PM6344 datasheet(22/256 Pages) PMC

22 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

Description

The PM6344 Quadruple E1 Framer (EQUAD) is a feature-rich device suitable for

use in many E1 systems with a minimum of external circuitry. Each of the

framers and transmitters is independently software configurable, allowing feature

selection without changes to external wiring.

On the receive side, the EQUAD recovers clock and data and can be configured

to frame to a basic G.704 2048 kbit/s signal or also frame to the signaling

multiframe alignment signal and the CRC multiframe alignment signal.

The EQUAD also supports detection of various alarm conditions such as loss of

signal, loss of frame, loss of signaling multiframe, loss of CRC multiframe, and

reception of remote alarm signal, remote multiframe alarm signal, alarm

indication signal, and timeslot 16 alarm indication signal. The EQUAD detects

and indicates the presence of remote alarm and AIS patterns and also integrates

red and AIS alarms as per industry specifications.

Performance monitoring with accumulation of CRC-4 errors, far end block errors,

framing bit errors, and line code violation is provided. The EQUAD also detects

and terminates HDLC messages on a data link. The data link may be extracted

from timeslot 16 and used for common channel signaling or may be extracted

from the national bits.

An elastic store for slip buffering and adaptation to backplane timing is provided,

as is a signaling extractor that supports signaling debounce, signaling freezing,

idle code substitution, digital milliwatt tone substitution, data inversion, and

signaling bit fixing on a per-channel basis. Receive side data and signaling trunk

conditioning is also provided.

On the transmit side, the EQUAD generates framing for a basic G.704 2048

kbit/s signal, or framing can be optionally disabled. The signaling multiframe

alignment structure may be optionally inserted and the CRC multiframe structure

may be optionally inserted.

Channel associated signaling insertion, idle code substitution, digital milliwatt

tone substitution, and data inversion on a per-timeslot basis is also supported.

Transmit side data and signaling trunk conditioning is provided.

HDLC messages on a data link can be transmitted. The data link may be

inserted into timeslot 16 and used for common channel signaling or may be

inserted into the national bits. The EQUAD can generate a low jitter transmit

clock and provides a FIFO for transmit jitter attenuation. When not used for jitter

PM6344 Datasheet(PDF) 22 Page - PMC-Sierra, Inc