PM6344 datasheet(16/256 Pages) PMC

16 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

Each one of four transmitter sections:

• Formats data to create a G.704 2048 kbit/s signal. Optionally inserts

signaling multiframe alignment signal. Optionally inserts CRC multiframe

structure including optional transmission of far end block errors.

• Optionally accepts dual rail digital PCM inputs to allow BPV transparency.

Also supports unframed mode and framing bit, CRC, or data link by-pass.

• Supports transfer of PCM and signaling data from 2.048 Mbit/s or

16.384Mbit/s backplane buses.

• Provides channel associated signaling insertion, programmable idle code

substitution, digital milliwatt code substitution, and data inversion on a per

timeslot basis.

• Provides trunk conditioning which forces programmable trouble code

substitution and signaling conditioning on all timeslots or on selected

timeslots.

• Supports transmission of the alarm indication signal (AIS), timeslot 16 AIS,

remote alarm signal or remote multiframe alarm signal.

• Provides an HDLC/LAPD interface for generating a data link. Supports

polled, interrupt-driven, or DMA servicing of the HDLC interface.

• Optionally inserts the data link into timeslot 16 (64 kbit/s), which may be used

to transmit common channel signaling, or into any combination of the national

bits in timeslot 0 of non-frame alignment signal frames (4 kbit/s - 20 kbit/s).

• Supports fractional E1 channel insertion.

• Provides a digital phase locked loop for generation of a low jitter transmit

clock.

• Provides a FIFO buffer for jitter attenuation and rate conversion in the

transmitter. FIFO full or empty indication allows for bit-stuffing in higher rate

multiplexing applications.

• Supports HDB3 or AMI line code.

• Provides dual rail or single rail digital PCM output signals.

PM6344 Datasheet(PDF) 16 Page - PMC-Sierra, Inc