PM6344 datasheet(78/256 Pages) PMC

78 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

Bit

Type

Function

Default

Bit 7

R/W

FIFOBYP

Bit 6

R/W

TAISEN

Bit 5

R/W

TDNINV

Bit 4

R/W

TDPINV

Bit 3

R/W

TUNI

Bit 2

R/W

FIFOFULL

Bit 1

R/W

TRISE

Bit 0

R/W

TRZ

This register enables the Transmit Interface to generate the required digital

output waveform format.

FIFOBYP:

The FIFOBYP bit enables the transmit bipolar input signals to DJAT to be

bypassed around the FIFO to the bipolar outputs. When jitter attenuation is

not being used the DJAT FIFO can be bypassed to reduce the delay through

the transmitter section by typically 24 bits. When FIFOBYP is set to logic 1,

the bipolar inputs to DJAT are routed around the FIFO and directly to the

bipolar outputs. When FIFOBYP is set to logic 0, the bipolar transmit data

passes through the DJAT FIFO.

Note that when FIFOBYP is set to a logic 1, the OCLKSEL1 bit in the

Transmit Timing Options register must also be set to logic 1.

TAISEN:

The TAISEN bit enables the interface to generate an unframed all-ones AIS

alarm on the TDP/TDD[x] and TDN[x] multifunction pins. When TAISEN is set

to logic 1 and TUNI is set to logic 0, the bipolar TDP[x] and TDN[x] outputs

are forced to pulse alternately, creating an all-ones signal; when TAISEN and

TUNI are both set to logic 1, the unipolar TDD[x] output is forced to all-ones.

When TAISEN is set to logic 0, the TDP/TDD[x] and TDN[x] multifunction

outputs operate normally. The transition to transmitting AIS on the TDP[x] and

TDN[x] outputs is done in such a way as to not introduce any bipolar

violations.

PM6344 Datasheet(PDF) 78 Page - PMC-Sierra, Inc

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