PM6344 datasheet(59/256 Pages) PMC

59 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

Figure 7

- DJAT Jitter Transfer

-10

-20

-30

-40

-50

100

10k

Jitter Frequency, Hz

Jitter Gain

(dB)

8.8

G.737, G738,

G.739, G.742

max

DJAT

response

Frequency Range

In the non-attenuating mode, that is, when the FIFO is within one UI of

overrunning or under running, the tracking range is 1.963 to 2.133 MHz. The

guaranteed linear operating range for the jittered input clock is 2.048 MHz ±

1278 Hz with worst case jitter (42 UIpp) and maximum XCLK frequency offset (±

100 ppm). The nominal range is 2.048 MHz ± 103 Hz with no jitter or XCLK

frequency offset.

8.13 Timing Options (TOPS)

The Timing Options block provides a means of selecting the source of the

internal input clock to the DJAT block, the reference signal for the digital PLL, and

the clock source used to derive the output TCLKO[x] signal.

8.14 Digital E1 Transmit Interface (DTIF)

The Digital E1 Transmit Interface provides control over the various output options

available on the multifunctional digital transmit pins TDP/TDD[x] and

TDN/TFLG[x]. When configured for dual-rail output, the multifunctional pins

become the TDP[x] and TDN[x] outputs. These outputs can be formatted as

either return-to-zero (RZ) or non-return-to-zero (NRZ) signals and can be

PM6344 Datasheet(PDF) 59 Page - PMC-Sierra, Inc