PM6344 datasheet(28/256 Pages) PMC

28 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

Pin Name

Type

Pin No.

Function

RDLSIG[1]

RDLSIG[2]

RDLSIG[3]

RDLSIG[4]/

Output

125

126

127

128

Receive Data Link Signal (RDLSIG[4:1]). The

RDLSIG[4:1] signals are available on these outputs

when the associated internal HDLC receiver (RFDL) is

disabled from use, or, optionally, when fractional E1 is

extracted. RDLSIG contains the data link stream

extracted from the selected data link bits. The EQUAD

may be configured to utilize timeslot 16 as a data link or

utilize any combination of the national bits as a data link.

Each RDLSIG[x] is updated on the falling edge of the

associated RDLCLK[x].

RDLINT[1]

RDLINT[2]

RDLINT[3]

RDLINT[4]

Receive Data Link Interrupt (RDLINT[4:1]). The

RDLINT[4:1] signals are available on these outputs

when the associated RFDL is enabled. Each RDLINT[x]

goes high when an event occurs which changes the

status of the associated HDLC receiver.

RDLCLK[1]

RDLCLK[2]

RDLCLK[3]

RDLCLK[4]/

Output

119

120

123

124

Receive Data Link Clock (RDLCLK[4:1]). The

RDLCLK[4:1] signals are available on these outputs

when the associated internal HDLC receiver (RFDL) is

disabled from use, or, optionally, when fractional E1 is

extracted. The rising edge of RDLCLK[x] can be used

to sample the data-link data or the fractional E1 data on

the associated RDLSIG[x] when the internal HDLC

receiver is disabled or when fractional E1 is enabled

respectively.

RDLEOM[1]

RDLEOM[2]

RDLEOM[3]

RDLEOM[4]

Receive Data Link End of Message (RDLEOM[4:1]).

The RDLEOM[4:1] signals are available on these

outputs when the associated RFDL is enabled. Each

RDLEOM[x] goes high when the last byte of a received

sequence is read from the associated RFDL FIFO

buffer, or when the FIFO buffer is overrun.

PM6344 Datasheet(PDF) 28 Page - PMC-Sierra, Inc

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