PM6344 datasheet(74/256 Pages) PMC

74 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

TXDMASIG:

The TXDMASIG bit selects the internal HDLC transmitter (XFDL) request for

service interrupt (INT) and data underrun (UDR) signals to be output on the

TDLINT[x] and TDLUDR[x] pins. When TXDMASIG is set to logic 1, the

TDLINT[x] and TDLUDR[x] output pins can be used by a DMA controller to

service the datalink. When TXDMASIG is set to logic 0, the XFDL INT and

UDR signals are no longer available to a DMA controller; the signals on

TDLINT[x] and TDLUDR[x] become the serial datalink data input and clock,

TDLSIG[x] and TDLCLK[x]. In this mode an external controller is responsible

for formatting the data stream presented on the TDLSIG[x] input to

correspond to the datalink in Time Slot 16 or the Time Slot 0 National Use

bits. If the TRAN block Configuration DLEN bit is logic 1 and the TRAN block

Configuration SIGEN bit is a logic 0, the TDLSIG data stream is inserted into

Time Slot 16 and the TDLCLK[x] pin is a 50% duty cycle 64 kHz clock;

otherwise, the TDLSIG[x] data stream is inserted into the Time Slot 0 National

Use positions enabled by the TXSAxEN bits. The TFRACE1 bit takes

precedent over TXDMASIG

In the default case TDLCLK[x] is a bursted 4 kHz clock and TDLSIG[x] is

inserted into the TS0 Sa4 bit.

TFRACE1:

The TFRACE1 bit selects whether a fractional E1 is inserted into a subset of

the channels of each frame via the TDLSIG[x] input, or whether the

TDLINT/TDLSIG[x] and TDLUDR/TDLCLK[x] pins operate as defined by the

TXDMASIG bit. When TFRACE1 is set to logic 1, the channel data is

expected on TDLSIG[x], sampled on the rising edge of a burst clock provided

on TDLCLK[x]. The channels inserted are determined by the Channel Select

registers; all others are inserted through BTPCM[x]. When TFRACE1 is set to

logic 0, the TDLINT/TDLSIG[x] and TDLUDR/TDLCLK[x] pins contain the

signals selected by the TXDMASIG bit.

RDLINTE:

The RDLINTE bit enables the RFDL received-data interrupt to also generate

an interrupt on the microprocessor interrupt, INTB. This allows a single

microprocessor to service the RFDL without needing to interface to the DMA

control signals. When RDLINTE is set to logic 1, an event causing an

interrupt in the RFDL (which is visible on the RDLINT output pin when

RXDMASIG is logic 1) also causes an interrupt to be generated on the INTB

output. When RDLINTE is set to logic 0, an interrupt event in the RFDL does

not cause an interrupt on INTB.

PM6344 Datasheet(PDF) 74 Page - PMC-Sierra, Inc

PM6344 Datasheet(HTML) 74 Page - PMC-Sierra, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL