PM6344 datasheet(81/256 Pages) PMC

81 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

Bit

Type

Function

Default

Bit 7

Unused

Bit 6

Unused

Bit 5

R/W

BTFPREF

Bit 4

Unused

Bit 3

R/W

BTXCLK

Bit 2

Unused

Bit 1

R/W

BTX2RAIL

Bit 0

R/W

BTXMFP

This register allows software to configure the Transmit backplane interface

format.

BTFPREF:

The BTFPREF bit selects the source of the input frame pulse. When

BTFPREF is set to logic 1, BTFP[1] is used as the input transmit frame pulse

for the associated interface. If BTFPREF is set to logic 0, BTFP[4:1] are used

as the input transmit frame pulses for the associated interface. Note that

when BTFPREF is set to a logic 1, the corresponding BTCLK[x] must be

phase aligned to BTCLK[1] to ensure proper sampling of BTFP[1].

The BTFPREF bit in register 005H has no effect if MENB is a logic 0. In this

case, MTFP is used to generate internal frame pulses for each quadrant.

BTXCLK:

The BTXCLK bit selects the source of the TRAN transmit clock input signal.

When BTXCLK is set to logic 1, the TRAN transmit clock is driven with the

2.048MHz recovered PCM output clock (RCLKO[x]) from the receiver

section. When BTXCLK is set to logic 0, the TRAN transmit clock is driven

with the 2.048MHz backplane transmit clock (BTCLK[x]).

BTX2RAIL:

The BTX2RAIL bit selects whether the backplane transmit data signal

presented to the transmitter on the multifunction inputs BTPCM/BTDP[x] and

BTSIG/BTDN[x] are in either dual-rail or single-rail format. When BTX2RAIL

is set to logic 1, the multifunction pins become the BTDP[x] and BTDN[x]

PM6344 Datasheet(PDF) 81 Page - PMC-Sierra, Inc

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