PM6344 datasheet(35/256 Pages) PMC

35 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

Pin Name

Type

Pin No.

Function

BTCLK[1]

BTCLK[2]

BTCLK[3]

BTCLK[4]

Input

Backplane Transmit Clock (BTCLK[4:1]). BTCLK[4:1]

are the 2.048MHz transmit clocks with optional gapping

for adaptation from non-uniform backplane data

streams. The EQUAD may be configured to ignore the

BTCLK[x] input and use the associated RCLKO[x] signal

in its place.

MTCLK

Multiplexed Transmit Clock (MTCLK). MTCLK shares a

pin with BTCLK[1]. BTCLK[4:2] are unused when the

multiplex enable (MENB) input is asserted low. When

the multiplex enable (MENB) input is asserted low, this

clock is 16.384 MHz. MTFP and MTD are sampled on

the rising edge of MTCLK.

TDLSIG[1]

TDLSIG[2]

TDLSIG[3]

TDLSIG[4]/

I/O

113

114

117

118

Transmit Data Link Signal (TDLSIG[4:1]). The

TDLSIG[4:1] signals are input on this pin when the

associated internal HDLC transmitter (XFDL) is disabled

from use, or if fractional E1 insertion is selected.

TDLSIG[x] is the source for the data stream to be

inserted into the selected data link bits. The EQUAD

may be configured to utilize timeslot 16 as a data link or

utilize any combination of the national bits as a data link.

If fractional E1 insertion is enabled, TDLSIG[x] is the

data source for the E1 channels enabled by the Channel

Select registers.

TDLSIG[x] is sampled on the rising edge of the

associated TDLCLK[x]. The TDLSIG[x] pins have

integral pull-ups.

TDLINT[1]

TDLINT[2]

TDLINT[3]

TDLINT[4]

Transmit Data Link Interrupt (TDLINT[4:1]). The

TDLINT[4:1] signals are output on these pins when the

associated XFDL is enabled. Each TDLINT[x] goes high

when the last data byte written to the XFDL has been

set up for transmission and processor intervention is

required to either write control information to end the

message, or to provide more data.

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