PM6344 datasheet(38/256 Pages) PMC

38 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

Pin Name

Type

Pin No.

Function

CSB

Input

Active low chip select (CSB). This signal must be low to

enable EQUAD register accesses. This signal must be

toggled high to clear the PMCTST register bit (register

00BH or 20BH) and to ensure the EQUAD will operate

in normal mode.

D[0]

D[1]

D[2]

D[3]

D[4]

D[5]

D[6]

D[7]

I/O

Bi-directional data bus (D[7:0]). This bus is used during

EQUAD read and write accesses.

RDB

Input

Active low read enable (RDB). This signal is pulsed low

to enable a EQUAD register read access. The EQUAD

drives the D[7:0] bus with the contents of the addressed

WRB

Input

Active low write strobe (WRB). This signal is pulsed low

to enable a EQUAD register write access. The D[7:0]

bus contents are clocked into the addressed normal

mode register on the rising edge of WRB while CSB is

low.

ALE

Input

Address latch enable (ALE). This signal latches the

address bus contents, A[9:0], when low, allowing the

EQUAD to be interfaced to a multiplexed address/data

bus. When ALE is high, the address latches are

transparent. ALE has an integral pull-up.

RSTB

Input

Active low reset (RSTB). This signal is set low to

asynchronously reset the EQUAD. RSTB is a Schmitt-

trigger input with integral pull-up.

A[0]

A[1]

A[2]

A[3]

A[4]

A[5]

A[6]

A[7]

A[8]

A[9]

Input

Address bus (A[9:0]). This bus selects specific registers

during EQUAD register accesses.

PM6344 Datasheet(PDF) 38 Page - PMC-Sierra, Inc

PM6344 Datasheet(HTML) 38 Page - PMC-Sierra, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL