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PM6344 Datasheet(PDF) 84 Page - PMC-Sierra, Inc |
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PM6344 Datasheet(HTML) 84 Page - PMC-Sierra, Inc |
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84 / 256 page  STANDARD PRODUCT PMC-Sierra, Inc. PM6344 EQUAD PMC-951013 ISSUE 5 QUADRUPLE E1 FRAMER 71 signal frames. The other enable bits operate in an analogous fashion. A clock pulse is generated on TDLCLK[x] for each enable that is logic 1. Any combination of enable bits is allowed, resulting in a data rate between 4 kbit/s and 20 kbit/s. Clearing all enable bits disables TS0 insertion. Any National Use bits which are not included in the data link are sourced from either BTPCM[x] or the TRAN block International/National Control register. Upon reset of the EQUAD, all bits are logic 0 except TXSA4EN. By default, a 4 kbit/s data link is inserted into Sa4 from the TDLSIG[x] input. |
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